Per-Module VTT Regulation for Memory Bus Power Management

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Solution Overview

Problem

Current memory module bus termination voltage (VTT) schemes oversize voltage regulators to accommodate maximum capacity, leading to increased costs and lack of per-module adjustment or power savings, as VTT is shared among all modules.

Innovation Solution

Implementing a memory module bus termination voltage regulation and management system where each module has its own voltage regulator, allowing for adjustable VTT based on actual loading and enabling per-module power management, such as gating the termination voltage to conserve power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a shared VTT supply connection is used for all memory modules, then the voltage regulator platform size is reduced, but the regulator must be oversized to accommodate maximum capacity, increasing cost

Engineering Contradiction:
Improvevoltage regulator platform sizeVSAvoidcost per host system
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent divides the shared VTT supply into separate per-module voltage regulator outputs, allowing each memory module to have its own dedicated voltage regulation. This segmentation enables the system to scale regulator capacity to actual usage rather than provisioning for maximum theoretical capacity, reducing overall system cost while maintaining the ability to support full memory capacity when needed.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a shared VTT supply connection is used for all memory modules, then device complexity is reduced, but per-module VTT adjustment is not possible

Engineering Contradiction:
ImproveVTT supply configurationVSAvoidper-module VTT adjustability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

By providing separate voltage regulator outputs for each memory module, the system enables independent VTT adjustment per module through memory controller registers. Each module's VTT can be individually programmed and adjusted without affecting other modules, providing fine-grained adaptability while maintaining relatively simple overall system architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local control of VTT parameters for each memory module through dedicated voltage regulator outputs and per-module configuration registers. This allows each module to have customized VTT settings optimized for its specific requirements, rather than forcing a uniform setting across all modules.

Inventive Principle:
Principle #3Local quality

3Device complexity

If a shared VTT supply connection is used for all memory modules, then device complexity is reduced, but power saving opportunities are lost due to inability to gate VTT per module

Engineering Contradiction:
ImproveVTT supply configurationVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The separate per-module voltage regulator outputs enable independent power management for each memory module. The system can gate or disable VTT supply to individual modules that are not currently in use, preventing unnecessary power consumption while maintaining VTT supply to active modules. This granular control allows the system to reduce overall power consumption dynamically based on actual memory usage patterns.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8649229B2Memory module bus termination voltage (VTT) regulation and management
Publication Date: 2014.02.11 TAHOE RES LTD
  • US8649229B2 patent drawing
  • US8649229B2 patent drawing
  • US8649229B2 patent drawing

AI summary

Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.