Per-Path Reference Voltage Training for High-Speed Memory Signaling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

At high-speed memory signaling rates above 3200 MT/s, signal degradation due to inter symbol interference (ISI) increases, causing the data eye to close and leading to bit error rate (BER) issues.

Innovation Solution

Implementing a feedback circuit that allows for reference voltage training and adjustment per path in memory devices, enabling optimal setting of receiver and transmitter reference voltages and timing delays for each data path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high speed memory signaling is used to increase data rates, then productivity is improved, but signal degradation increases due to inter symbol interference

Engineering Contradiction:
Improvedata rateVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the data stream into multiple paths (e.g., even and odd paths) and processes each path separately with dedicated reference voltage training. This segmentation allows independent optimization of each path to compensate for signal degradation at high data rates, maintaining reliability while achieving high productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements path-specific reference voltage training where each data path receives customized reference voltage settings based on its individual characteristics. This local quality approach ensures that each path is optimized for its specific signal conditions, improving overall signal quality at high data rates without compromising productivity.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If reference voltage training is implemented per path, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage setting accuracyVSAvoidtraining circuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The training circuit is segmented into path-specific training modules that operate independently. Each module handles reference voltage training for a specific data path, simplifying the design of individual modules while achieving high overall precision through the coordinated operation of multiple segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Reference voltage training is performed in advance during the initialization phase before normal data transmission begins. This preliminary action establishes optimal voltage settings for each path beforehand, ensuring high manufacturing precision without adding complexity to the ongoing data transmission operation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If data eye width is maintained through training, then reliability is improved, but loss of time increases due to training overhead

Engineering Contradiction:
Improvebit error rateVSAvoidtraining time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Reference voltage training and path optimization are performed during the initialization phase before normal data transmission begins. This preliminary action ensures that all paths are properly calibrated in advance, maintaining high reliability during operation without causing time loss during actual data transfer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Once training is complete, the optimized reference voltage settings are maintained continuously during normal operation, ensuring consistent data eye width and reliability. The training process establishes long-term optimal settings that eliminate the need for repeated training interruptions.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12204751B2Reference voltage training per path for high speed memory signaling
Publication Date: 2025.01.21 INTEL CORP
  • US12204751B2 patent drawing
  • US12204751B2 patent drawing
  • US12204751B2 patent drawing

AI summary

In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.