Per-Pin Clock Synthesis for Low-Jitter IC Test Timing
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Solution Overview
Problem
Current Automated Test Equipment (ATE) systems face challenges in achieving precise phase and frequency synchronization across multiple channels, particularly when testing Integrated Circuits (ICs), leading to issues with jitter and noise pickup, which affect the accuracy of IC testing.
Innovation Solution
The solution involves central generation of a reference frequency and super-period clock, distributed to individual pins for pin-individual clock synthesis, allowing for precise control of frequency, phase, and amplitude modulation, with synchronization integrated within the test signal processor, minimizing jitter and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency reference is provided centrally with synchronized master clocks distributed to cards, then frequency synchronization is improved, but phase synchronization precision and control flexibility deteriorate
Solution Approach 1:
The system divides clock synthesis into two segments: central frequency reference generation and local per-pin phase synthesis. The central unit generates the frequency reference and distributes it to multiple cards, while each card independently synthesizes pin-specific clock signals with individual phase control. This segmentation resolves the contradiction by maintaining frequency synchronization centrally while enabling phase flexibility locally at each pin.
Solution Approach 2:
The patent implements local quality by allowing each pin to have its own phase offset parameter while sharing the same frequency reference. The per-pin clock synthesis unit adjusts phase locally for each pin individually, enabling precise phase control adaptability at the pin level without compromising the centrally-synchronized frequency reference distribution across all cards.
2Stability of the object's composition
If clock signals are distributed centrally to cards, then system synchronization is improved, but jitter and noise pickup increase
Solution Approach 1:
The system performs preliminary action by generating the frequency reference centrally in advance and distributing it to all cards before local clock synthesis occurs. Each card then independently synthesizes its clock signals from this pre-distributed reference, minimizing the time clock signals travel through distribution networks and reducing exposure to jitter and noise during transmission while maintaining system-wide synchronization.
Solution Approach 2:
The centrally-generated frequency reference acts as an intermediary between the central control system and local pin-specific clock synthesis units. This intermediary reference signal enables each card to generate its own clean clock signals locally without requiring direct distribution of final clock signals across the system, thereby reducing jitter and noise pickup while maintaining synchronization through the common reference.
3Speed
If fast digital-to-analog converters are used for high-speed clock signals, then clock speed is improved, but cost and performance limitations increase
Solution Approach 1:
The patent replaces the need for fast digital-to-analog converters with a direct digital synthesis approach. Instead of converting digital clock signals to analog using high-speed DACs, the system generates pin-specific clock signals digitally at each pin location through per-pin clock synthesis. This substitution eliminates the requirement for expensive fast DAC hardware while achieving the same high-speed clock signal generation function through digital signal processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in low jitter, high-speed clock signals with reduced noise pickup, enhancing the accuracy and reliability of IC testing by ensuring clean clock signals and avoiding cost and performance limitations associated with fast digital-to-analog converters.
Implementation Method 1
synchronization integrated within the test signal processor, minimizing jitter and noise
Data Source
AI summary
A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic circuit having a test signal processor controlling electrically said pins of said device under test with predetermined signal pattern, characterized by synthesizing locally at said test signal processor a digital clock signal, said digital clock signal being individual for said pin of said device under test electrically controlled by said test signal processor.