3D Per-Pixel Single-Slope ADC Layout for Ultra-High Frame Rates
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Solution Overview
Problem
Conventional single slope analog-to-digital converters (SS-ADCs) in electro-optical sensors face limitations in low power environments and are constrained by the need for sequential conversion of pixels, which restricts maximum frame rate, especially as array size increases, due to analog-to-digital conversion being performed at the column level.
Innovation Solution
The SS-ADC is designed with a comparator in one layer and a counter in a separate layer, electrically connected via a through silicon via (TSV), allowing for massively parallel conversion of all pixels simultaneously, with the comparator and counter formed using different semiconductor process nodes and connected using direct bond integration (DBI) for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog-to-digital conversion is performed at the column level using conventional SS-ADC designs, then device complexity is reduced and ease of manufacture is improved, but maximum frame rate is limited and conversion time increases as array size increases
Solution Approach 1:
The converter is divided into multiple independent conversion units, each capable of converting analog signals from different columns simultaneously. This segmentation allows parallel processing of multiple pixel signals, increasing the maximum frame rate without proportionally increasing overall device complexity, as each unit operates independently but can be implemented using standardized circuit blocks
Solution Approach 2:
The patent transitions from sequential column-level conversion to spatially distributed parallel conversion across multiple columns. By adding the dimension of spatial parallelism (converting multiple columns at once rather than one after another), the system achieves higher frame rates while managing complexity through modular architecture
2Loss of time
If sequential conversion of pixels is used at column level, then manufacturing is simplified, but conversion time increases and frame rate is restricted especially as array size increases
Solution Approach 1:
The conversion process is segmented into multiple parallel operations occurring simultaneously in different conversion units. Each unit handles a specific column or group of columns, reducing total conversion time from sequential to parallel execution while maintaining manufacturability through modular design that can be replicated across the array
Solution Approach 2:
Multiple conversion units are pre-configured and ready to operate simultaneously, eliminating the need to sequence conversion operations. The parallel architecture allows all active columns to be converted at the same time, significantly reducing conversion time while the modular nature preserves ease of manufacture
3Power
If conventional SS-ADC designs are used in low power environments, then device simplicity is maintained, but power efficiency is insufficient and frame rate capabilities are limited
Solution Approach 1:
The power consumption is distributed across multiple independent conversion units that can operate in parallel. Each unit can be independently controlled and powered down when not needed, improving overall power efficiency. The segmented architecture allows selective activation of only the necessary conversion units based on the number of active columns, reducing total power consumption while managing complexity through modular design
Data Source
AI summary
An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.