Per-Processor Memory Areas with Virtual Aliases
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Solution Overview
Problem
In multi-processor systems, existing technologies face challenges in ensuring safe, non-preemptible access to per-CPU private data areas (PRDAs) across different CPU architectures, particularly where atomic instructions are not supported, leading to potential race conditions and performance overhead due to interrupt disabling.
Innovation Solution
The implementation of a computer system that uses a common virtual address to access PRDAs, ensuring safe execution by blocking preemption until non-preemptible code completes, and migrating contexts between CPUs while using a designated virtual address to maintain access to the correct PRDA, even across CPU migrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt disabling is used to ensure non-preemptible access to PRDA, then access safety is improved, but performance overhead increases
Solution Approach 1:
The system segments the address space by creating per-CPU private data areas (PRDAs) that are uniquely associated with each CPU. This segmentation allows each CPU to access its own dedicated data area without interference from other CPUs, eliminating the need for interrupt disabling while maintaining access safety.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of CPU-specific address translation or mapping that mediates access to PRDAs. This intermediary ensures that each CPU accesses only its designated data area through address translation, providing safety without requiring interrupt disabling and thus avoiding performance overhead.
2Ease of operation
If atomic instructions are assumed to be available, then non-preemptible access is simplified, but portability to architectures without atomic instructions deteriorates
Solution Approach 1:
The system implements a universal mechanism for non-preemptible access that works across different CPU architectures. By using CPU-specific data areas with unique addresses that are valid across all architectures, the solution provides architecture-independent portability while maintaining access simplicity equivalent to atomic instructions.
Solution Approach 2:
The patent creates copies of the same data structure (PRDA) in each CPU's address space, with each copy having a unique CPU-specific address. This copying approach allows the same access pattern to work universally across different architectures without requiring architecture-specific atomic instructions, thereby improving portability while maintaining simplicity.
3Adaptability or versatility
If context migration between CPUs is allowed, then system flexibility is improved, but PRDA access safety deteriorates due to potential access to wrong CPU's data area
Solution Approach 1:
The system applies local quality by making each PRDA uniquely associated with its owning CPU through CPU-specific addressing. When a context migrates between CPUs, the address translation mechanism ensures that the context automatically accesses the PRDA of the new CPU, maintaining both migration flexibility and access safety through localized address binding.
Solution Approach 2:
The patent implements dynamic address binding where the mapping between virtual addresses and physical PRDA addresses changes based on the current CPU context. This dynamic mechanism allows contexts to migrate freely between CPUs while automatically accessing the correct PRDA for each CPU, thereby maintaining both flexibility and safety simultaneously.
Data Source
AI summary
A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.