Perceptron-Based Hardware Obfuscation for Trojan-Resistant ICs
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Solution Overview
Problem
Current integrated circuit (IC) security methods are inadequate in preventing reverse engineering and Trojan insertion, as existing obfuscation techniques do not provide sufficient protection against adversaries once the chip is in their possession, allowing for extraction of hardware design and potential modification.
Innovation Solution
The proposed method integrates trainable logic blocks (TLBs) with a perceptron-inspired architecture for logic gate and interconnect obfuscation, using a training-based approach that generates patterns to obscure chip functionality, eliminating the need for programmable read-only memory (PROM) and enhancing security through floating gate transistors and nonvolatile memory (NVM) for secure configuration and fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If traditional obfuscation techniques are used to hide chip functionality, then reverse engineering resistance is improved, but security protection against Trojan insertion deteriorates
Solution Approach 1:
The patent applies preliminary action by training the perceptron network before the chip is deployed to the adversary. The training phase configures the weight values and establishes the functional behavior in advance, so that when the chip is later possessed by an adversary, the obfuscation is already in place and cannot be easily reversed or bypassed, providing both reverse engineering resistance and Trojan protection
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the weight values in the perceptron network through training. These weight parameters determine the logic gate functionality and interconnect behavior. By changing these parameters during training, the chip functionality is obfuscated in a way that resists both reverse engineering and Trojan insertion, as the adversary cannot determine the actual logic function from the physical structure alone
2Reliability
If perceptron-inspired obfuscation is implemented to enhance security, then Trojan insertion protection is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single perceptron network structure that serves multiple functions: it provides logic gate obfuscation, interconnect obfuscation, and Trojan insertion protection all through the same training mechanism. This multi-functional approach enhances security against multiple threats without proportionally increasing complexity, as the same structural elements perform multiple security functions
Solution Approach 2:
The patent uses self-service by implementing a training mechanism that automatically configures the obfuscation parameters without requiring manual intervention or external programming. The perceptron network trains itself on provided training data to establish the obfuscated functionality, reducing the complexity of configuration and deployment while maintaining strong Trojan protection
3Difficulty of detecting and measuring
If training-based obfuscation is used to obscure chip functionality, then security against reverse engineering is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by completing the training process during or before the manufacturing phase. The weight values and configuration parameters are established in advance through training on training data, so that the final chip product already contains the obfuscated functionality. This preliminary training action ensures that functionality extraction is difficult for adversaries while the manufacturing process itself remains relatively simple, as the training can be automated
Data Source
AI summary
The method for obfuscating hardware partially imitates the neural network perceptron, obfuscating the hardware design. This method obfuscates the design functionality and immunes integrated circuits against Trojan insertion. This method can also be used to check for the existence of faults inside chips. This method resolves the concern related to security and reliability when outsourcing the manufacture of integrated circuits.