Per-core Voltage and Frequency Control via Effective Utilization
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Solution Overview
Problem
Conventional power state selection in computing devices based solely on core utilization can lead to sub-optimal performance due to thread migration across multiple cores, as it does not account for the overall process utilization, resulting in inadequate frequency selection.
Innovation Solution
The implementation of an effective core utilization determination circuitry that considers both core and process utilization, based on a performance or energy efficiency bias indicator, to select an appropriate power state for processing cores, ensuring optimal frequency selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power state selection is based solely on core utilization, then the selection process is simple, but performance becomes sub-optimal due to thread migration not being accounted for
Solution Approach 1:
The patent segments the utilization measurement into two distinct components: core utilization (local thread execution on a specific core) and process utilization (total execution time across all cores). This segmentation allows the system to independently track and evaluate each aspect, resolving the contradiction by maintaining measurement simplicity while achieving comprehensive performance optimization through the combined metric.
Solution Approach 2:
The patent introduces a new dimension to the power state selection problem by adding process utilization as an additional factor beyond core utilization. This dimensional expansion transforms the selection criteria from a single-dimensional (core-only) approach to a multi-dimensional approach that considers both local core activity and overall process execution, thereby improving performance without excessively complicating the selection process.
2Ease of operation
If frequency is selected based on core utilization only, then the selection is straightforward, but thread migration causes performance hits
Solution Approach 1:
The patent implements a feedback mechanism that continuously monitors both core utilization and process utilization to dynamically adjust frequency selections. By incorporating process utilization feedback, the system can detect thread migration patterns and adjust frequencies accordingly, maintaining performance stability while keeping the selection process operationally simple through automated adaptive control.
Solution Approach 2:
The patent applies preliminary action by proactively adjusting frequency based on predicted process utilization patterns before thread migration performance hits occur. The system anticipates migration events by monitoring process-level execution patterns and pre-adjusts frequencies to maintain optimal performance, preventing rather than reacting to performance degradation.
3Productivity
If per-core voltage and frequency domains are implemented, then throughput performance increases, but power management complexity increases
Solution Approach 1:
The patent applies local quality by enabling different voltage and frequency domains for different cores based on their specific utilization characteristics. Each core can operate at optimized local settings rather than uniform global settings, improving throughput performance while managing power consumption locally. This resolves the contradiction by allowing performance optimization without requiring system-wide complexity increases.
Solution Approach 2:
The patent implements dynamics by making voltage and frequency settings adaptive rather than static. The system dynamically adjusts per-core power states based on real-time core utilization and process utilization patterns, allowing the power management to respond to changing workloads. This dynamic approach improves throughput while managing complexity through automated adaptive control rather than rigid configuration.
Data Source
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Figure 1B
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AI summary
An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.