Perforated Capture Pad Structure for TSV Etching Control
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Solution Overview
Problem
The formation of through silicon vias (TSVs) in semiconductor devices often results in undesirable over-etching and potential damage to integrated circuitry due to uncontrolled etching processes, leading to contamination and shorts between metal interconnect layers.
Innovation Solution
A semiconductor package design featuring a first pad with perforations aligned with a second pad, where the conductive via penetrates through the substrate and contacts the first pad, preventing etchant contamination by terminating at the second pad's solid portions, thus controlling the etching process and preventing shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the etching process to form the through silicon via is not carefully controlled, then the etching speed increases and productivity improves, but the etchant will contaminate the wafer and cause damage to the integrated circuit
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the etchant and the integrated circuit. This layer allows the etchant to pass through during the etching process while protecting the underlying circuitry from contamination and damage. The sacrificial layer is selectively removed after etching, having served its protective function.
Solution Approach 2:
The capture pad structure with through-holes is prepared in advance before the etching process. This preliminary structuring enables the etchant to flow through controlled paths during etching, preventing uncontrolled contamination while maintaining high etching speed.
2Productivity
If the etching process is aggressive to improve productivity, then the through silicon via formation speed increases, but the conductive metal layer may extend to another metal interconnect layer creating shorts
Solution Approach 1:
The capture pad with its through-hole structure acts as an intermediary that guides the etchant flow. It allows aggressive etching to proceed quickly while the structured openings ensure the conductive layer terminates precisely at the intended location, preventing extension into adjacent interconnect layers.
Solution Approach 2:
The capture pad structure provides locally differentiated properties - solid regions that block etchant and through-holes that permit etchant flow. This local quality variation enables precise control of etching boundaries, ensuring conductive layers terminate exactly where needed while maintaining high overall etching speed.
3Ease of manufacture
If the etchant fluid passes through perforations in the capture pad during etching, then the etching process can proceed, but this results in undesirable over-etching and potential damage to the circuitry
Solution Approach 1:
The sacrificial layer serves as a mediator that allows etchant to pass through the capture pad perforations during etching while preventing the harmful effects of over-etching. After etching is complete, the sacrificial layer is removed, having protected the circuitry during the manufacturing process.
Solution Approach 2:
The sacrificial layer provides beforehand cushioning or protection during the etching process. It absorbs the potential harmful effects of uncontrolled etchant flow through the capture pad, preventing damage to the integrated circuit while allowing the etching to proceed.
Data Source
AI summary
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.