Perforated Channel FET Reducing On-Resistance and Capacitance
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Solution Overview
Problem
Conventional field-effect transistors face limitations in achieving low on-resistance and low input/output capacitances simultaneously due to the trade-off between these characteristics and operating voltage, leading to increased power losses in power switches and amplifiers.
Innovation Solution
The introduction of perforations under the gate in the semiconductor channel of a field-effect transistor design, which extends beyond the channel location, reduces the on-state resistance and input/output capacitances, thereby improving the RONCIN and RONCOUT products below theoretical limits for conventional FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the total gate width is increased to decrease on-resistance, then the on-resistance decreases, but the gate capacitance and gate charge increase, which increases switching loss
Solution Approach 1:
The gate is segmented into multiple fingers with perforations between them, dividing the continuous gate structure into discrete segments. This segmentation allows the gate to maintain effective width for low on-resistance while reducing the overlapping area that contributes to gate capacitance and gate charge, thereby reducing switching loss.
Solution Approach 2:
Perforations are introduced into the gate structure, creating a porous or hollow gate design. This reduces the effective gate area that contributes to capacitance while maintaining the electrical conductivity path for current flow, achieving low on-resistance with reduced gate capacitance and switching loss.
2Shape
If the gate-drain distance is shortened to decrease on-resistance, then the on-resistance decreases, but the maximum device operating voltage is reduced
Solution Approach 1:
The gate structure transitions from a planar two-dimensional configuration to a three-dimensional hollow or perforated structure. This dimensional change allows the gate to maintain electrical effectiveness for low on-resistance while reducing the physical footprint and electric field overlap with the drain, preserving breakdown voltage and operating voltage capability.
3Shape
If the total gate width is increased to decrease on-resistance, then the on-resistance decreases, but the input and output capacitances increase
Solution Approach 1:
The gate is divided into multiple segmented fingers with perforations, reducing the continuous overlapping area between gate and source/drain regions. This segmentation maintains the effective gate width for current conduction while reducing the capacitive coupling area, achieving low on-resistance with reduced input and output capacitances.
Solution Approach 2:
The hollow or perforated gate structure reduces the effective dielectric overlap volume between gate and channel regions, thereby reducing parasitic capacitances while maintaining the conductive path width needed for low on-resistance operation.
Data Source
AI summary
A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the semiconductor structure below the gate contact. Furthermore, a perforation in the plurality of perforations can extend into the semiconductor structure beyond a location of the semiconductor channel.