Perforated Semiconductor Device With Metal-Filled TSVs
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Solution Overview
Problem
Existing semiconductor device manufacturing processes, such as wire bonding and flip chip, face inefficiencies in electrical connectivity and high costs due to the use of wires and Under Ball Metal (UBM) bumps, which hinder the integration of high power devices in compact areas.
Innovation Solution
A semiconductor device with perforated sidewalls and a patterned back-side-metallization layer, where metal coating fills the perforations to provide electrical connections between die pads and isolated regions, allowing direct bonding to a circuit board without wires or bumps, utilizing Through-Silicon-Vias (TSV) and Solder Surface-Mount-Technology (SMT) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding process is used, then electrical connection is provided, but electrical efficiency deteriorates due to long and thin wires
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections through TSVs (Through-Silicon Vias). The conductive paths extend through the thickness of the semiconductor substrate, creating direct vertical routes that dramatically reduce the effective connection length and improve electrical efficiency compared to traditional lateral wire bonds
Solution Approach 2:
The patent introduces TSVs as intermediary conductive structures that mediate the connection between top surface pads and bottom surface contact pads. These TSVs act as vertical conduits that replace long lateral wire paths with short vertical metal-filled vias, thereby improving electrical efficiency while maintaining design flexibility
2Reliability
If flip chip process is used, then electrical connection is provided, but manufacturing cost increases due to added cost of FC under ball metal and bump process
Solution Approach 1:
The patent extracts and eliminates the complex UBM (Under Ball Metal) and bump formation processes from the manufacturing flow. Instead of requiring multiple metallization layers and spherical bump structures, the design uses simple TSVs that extend directly through the substrate, removing unnecessary manufacturing steps and reducing costs
Solution Approach 2:
The patent changes the fundamental connection parameter from spherical bumps to cylindrical or rectangular TSV cross-sections. This parameter change simplifies the manufacturing process by eliminating the need for bump formation equipment and UBM deposition, while maintaining effective electrical and thermal connections
3Reliability
If traditional packaging is used, then device protection is provided, but device footprint increases due to encapsulation
Solution Approach 1:
The patent extracts the semiconductor device from traditional encapsulated packaging and presents it as a bare die with exposed top and bottom surfaces. The TSV structure provides inherent protection and functionality without requiring additional molding compound or packaging materials, thereby minimizing the device footprint
Solution Approach 2:
The TSV structure serves multiple functions simultaneously: it provides electrical connection, thermal management pathways, and mechanical support. This multi-functionality eliminates the need for separate packaging components that would otherwise be required for protection and heat dissipation, reducing overall device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces resistive-capacitive delay, lowers costs by eliminating the need for UBM bumps, and enhances thermal efficiency through signal routing and heat dissipation, making it suitable for high power and RF devices with a smaller footprint compared to encapsulated packages.
Implementation Method 1
metal coating partially filling the perforations and providing electrical connection between respective ones of the plurality of die pads and respective ones of the plurality of electrically isolated regions
Implementation Method 2
enhances thermal efficiency through signal routing and heat dissipation
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a die having a central active region, a top surface, a bottom surface, and sidewalls having a plurality of perforations therein, each perforation extending from a top end at the top surface to a bottom end at the bottom surface; a plurality of die pads on the top surface and extending from the central active region to respective top ends; a patterned back-side-metallization layer on the bottom surface, comprising a plurality of electrically isolated regions extending to respective bottom ends; metal coating partially filling the perforations and providing electrical connection between respective ones of the plurality of die pads and respective ones of the plurality of electrically isolated regions; and a passivation layer covering the top surface and the die pads.