Performance-Aware Logic Operations for Mask Design
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Solution Overview
Problem
Conventional logic operations in lithography processes for integrated circuit manufacturing are inflexible, limiting the ability to improve device performance by not allowing adjustable sizes of stressed contact etch stop layers, which restricts the optimization of PMOS and NMOS transistor performance.
Innovation Solution
The use of performance-aware logic operations to design masks with stressor layers that apply compressive and tensile stresses to channel regions of PMOS and NMOS transistors, respectively, allowing for customizable sizes and shapes to optimize device performance without violating design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional logic operations are used to design masks with stressor layers, then design rules are followed, but the sizes of stressor layers cannot be adjusted to optimize device performance
Solution Approach 1:
The patent implements dynamic logic operations that allow stressor layer sizes to be adjusted based on performance requirements. The system transitions from static, fixed-size stressor layers to dynamic, adjustable sizes through iterative logic operations that expand or contract layer dimensions while maintaining design rule compliance.
Solution Approach 2:
The patent changes the parameter of stressor layer size from a fixed value to an adjustable variable. By modifying the size parameter iteratively through logic operations, the system optimizes device performance while adhering to design constraints, enabling flexible control over stressor layer dimensions.
2Reliability
If stressor layer sizes are increased to improve device performance, then drive currents are optimized, but chip area usage increases
Solution Approach 1:
The patent applies local quality by selectively adjusting stressor layer sizes only in specific regions where performance optimization is needed, rather than uniformly increasing all stressor layers. This allows targeted improvement of drive currents in critical areas while maintaining minimal chip area usage in non-critical regions.
Solution Approach 2:
The patent implements partial action by applying stressor layer expansion only to the extent necessary for performance optimization. The iterative logic operations determine the minimum required size for each stressor layer, avoiding excessive area usage while achieving sufficient performance improvement.
3Ease of manufacture
If conventional mask design methods are used, then manufacturing processes are simple, but performance optimization is limited
Solution Approach 1:
The patent implements self-service through automated iterative logic operations that automatically adjust stressor layer sizes based on performance criteria. The system performs self-optimization without requiring complex manual intervention, maintaining ease of manufacture while achieving performance optimization through algorithmic design adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible mask design and improved performance of integrated circuits without increasing chip area usage, allowing for optimized drive currents and global performance by iteratively adjusting stressor layer sizes and shapes.
Implementation Method 1
the first stressor layer has a compressive stress
Implementation Method 2
the second stressor layer has a tensile stress
Data Source
AI summary
Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.