TVS Package Structure Using Perimeter Ridges for Solder Overflow Control
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Solution Overview
Problem
The packaging of semiconductor devices, particularly large area semiconductor dies used in transient-voltage-suppression (TVS) applications, faces challenges with solder paste curing, as it can lead to overflow issues due to the solder running to the chip edges during assembly.
Innovation Solution
A package structure and method that includes a lead frame with a perimeter ridge defining a recessed area to contain solder, and a clip with a similar design to abut the chip layer, ensuring the solder is constrained and preventing overflow, while connecting a transient-voltage-suppression device to the pedestal using solder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If solder paste is applied to connect the semiconductor die to the substrate, then electrical and mechanical connection is achieved, but the solder paste can run to the chip edge and cause overflow issues
Solution Approach 1:
The substrate is segmented into multiple regions including a recessed area that physically separates the solder application zone from the chip edge. This segmentation prevents solder from running uncontrollably to the chip edge while maintaining effective electrical and mechanical connection between the die and substrate.
Solution Approach 2:
A solder resist layer is introduced as an intermediary substance between the solder paste and the substrate surface. This layer selectively prevents solder from flowing into unwanted areas while allowing it to adhere properly to the die and substrate connection points, thus controlling solder placement precision without compromising connection strength.
2Power
If larger semiconductor dies are used to provide greater current handling, then power requirements are met, but solder paste overflow issues become more severe
Solution Approach 1:
The substrate incorporates a recessed area that segments the solder application region, creating a physical boundary that contains solder within a controlled zone. This segmentation becomes increasingly important for larger dies with greater current handling requirements, as it prevents solder overflow that would be more problematic with larger device footprints.
Solution Approach 2:
The solder resist layer serves as a mediator that manages solder flow behavior across the entire substrate surface. For larger semiconductor dies, this intermediary control mechanism is essential to prevent solder from spreading beyond the intended connection areas, thereby eliminating the proportional increase in overflow risk that comes with larger device sizes.
3Reliability
If multiple chips are connected in series in a stacked configuration to provide high breakdown voltage, then TVS device performance is achieved, but assembly complexity increases
Solution Approach 1:
The substrate is segmented into multiple connection regions and recessed areas that are specifically designed to accommodate stacked chip configurations. Each chip in the series connection can be positioned in its own designated area with controlled solder zones, simplifying the assembly process despite the increased number of components and connections required to achieve high breakdown voltage.
Data Source
AI summary
Provided herein are package structures including a first lead frame having a first pedestal and a first lead extending from the first pedestal. A first perimeter ridge defines a first recessed area in a first main side of the first pedestal, wherein a die pad is positioned within the first recessed area. The package structure may further include a chip layer having a first main side opposite a second main side, wherein the second main side is in abutment with the first perimeter ridge of the pedestal of the first lead frame. The package structure may further include a clip including a second pedestal and a lead connector extending from the second pedestal, wherein a second perimeter ridge defines a second recessed area in a second main side of the second pedestal, and wherein the second perimeter ridge is in abutment with the first main side of the chip layer.