Periodic DC Offset Compensation in RF Baseband Demodulation
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Solution Overview
Problem
Conventional RF receiver chips face challenges in accurately estimating and compensating for DC offsets within short time frames, particularly in high-data rate communication schemes like 802.11a/g/n, where the preamble is too short for prior art DC offset adjustment circuits to produce reliable estimates.
Innovation Solution
A DC offset adjustment circuit that uses a filter to estimate DC offsets based on digital samples within a sample period equal to the signal's periodicity, combined with a low pass filter to smooth the estimate, allowing for effective DC offset removal even in zero-mean periodic signals, and dynamic switching between different loops for efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DC offset adjustment circuit with feedback loop and weighting factor is used, then the circuit can estimate DC offset over time, but it requires sufficient time (150-200 microseconds) to produce an accurate estimate, which is too long for short preambles in 802.11a/g/n (8 microseconds)
Solution Approach 1:
The patent applies preliminary action by using the periodic structure of the preamble signal itself to pre-estimate the DC offset before data reception. The method exploits the known periodicity (e.g., 0.8 microseconds in 802.11a/g/n) to calculate DC offset from a single period or few periods of the preamble, eliminating the need for prolonged feedback loops. This allows accurate DC offset compensation to be performed in advance, within the 8 microsecond preamble duration, rather than requiring 150-200 microseconds of continuous sampling.
2Speed
If the weighting factor alpha is made large (close to 1) to emphasize current samples, then faster response is achieved, but less weight is placed on average value reducing estimation reliability; conversely, if alpha is small (close to 0) to emphasize average value, then estimation stability improves but response time increases
Solution Approach 1:
The patent applies parameter changes by fundamentally altering the estimation approach from a time-averaging feedback loop to a periodic-signal-based calculation. Instead of adjusting the weighting factor alpha in a recursive formula, the method changes the parameter being measured (utilizing the periodic structure at frequency f0) and the calculation methodology (using correlation or averaging over integer periods). This parameter transformation enables both fast response (within one period) and high reliability (based on known signal structure) simultaneously.
3Measurement precision
If DC offset compensation is performed using prior art methods with long preambles, then accurate estimation is achieved, but the method is not suitable for high-data rate schemes with short preambles where time is limited
Solution Approach 1:
The patent applies dynamics by making the DC offset estimation method adaptive to different preamble structures and durations. The system dynamically selects appropriate estimation techniques based on the detected signal period and available time. For short preambles in high-data-rate modes (802.11a/g/n), it uses periodicity-based estimation over 0.8 microsecond periods. For longer preambles (802.11b), it can use traditional methods. This dynamic adaptation enables accurate DC offset compensation across different productivity requirements.
Data Source
AI summary
An apparatus has demodulation circuitry to demodulate a radio frequency signal and produce a baseband signal, wherein the radio frequency signal comprises a periodic signal having a predetermined period. An analog-to-digital converter converts the baseband signal into a digital signal that comprises a periodic signal having the predetermined period. A first DC offset adjustment circuit estimates a DC offset contained in the digital signal based on digital samples in a sample period having a length equal to the predetermined period. A second DC offset adjustment circuit estimates the DC offset contained in the digital signal. A selection circuit selects one of the first DC offset adjustment circuit or the second DC offset adjustment circuit to be used to estimate the DC offset contained in the digital signal.