Peripheral Bus Address-Space Bridging for Cross-Component Data Transfer
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Solution Overview
Problem
Existing computing systems are limited by the inability of peripheral devices to access memory address spaces of system components other than the one they are directly assigned to, hindering efficient collaboration and data transfer between components.
Innovation Solution
The system enables peripheral devices to access and transfer data across multiple address spaces by associating address translations using Memory Keys (MKEYs) and Translation and Protection Tables (TPTs), allowing one system component to control data access for another, with security policies governing these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If peripheral devices are restricted to access only their assigned system component's address space, then security and simplicity are maintained, but data transfer efficiency and collaboration between components deteriorate
Solution Approach 1:
The patent introduces an address translation association mechanism that acts as an intermediary, allowing peripheral devices to access address spaces of system components other than their assigned one. The Translation and Protection Table (TPT) and Memory Key (MKEY) association create a controlled bridge between the peripheral device's address space and the target system component's address space, enabling efficient data transfer while maintaining security through verification of permitted access.
2Adaptability or versatility
If peripheral devices can access multiple address spaces, then collaboration between system components improves, but security risks and access control complexity increase
Solution Approach 1:
The address translation association mechanism serves as a security intermediary that verifies and controls access between peripheral devices and multiple system components. The TPT stores associations between MKEYs of different system components, and the peripheral device must verify permitted access through this association before accessing another component's address space, thereby enabling collaboration while maintaining security.
Solution Approach 2:
The system implements feedback through the address translation association verification process. Before a peripheral device can access an address space of a system component other than its assigned one, the system checks the TPT to verify that the access is permitted according to security policies. This feedback mechanism ensures that only authorized cross-address-space accesses are allowed.
3Speed
If address space access is tightly coupled to system component assignment, then system simplicity is maintained, but data transfer speed and operational efficiency decrease
Solution Approach 1:
The system performs preliminary action by pre-establishing address translation associations in the TPT between MKEYs of different system components. This allows peripheral devices to directly access address spaces of other system components without real-time translation overhead, thereby enabling fast data transfer while the complexity of managing these associations is handled in advance by the system.
Data Source
AI summary
A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.