Peripheral Device Address Translation Sharing
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Solution Overview
Problem
Current virtual memory addressing techniques for I/O devices require significant coordination between the I/O device and the host operating system, leading to overhead and data transfer latency due to the need for handling page faults and updating translation tables.
Innovation Solution
A method where a peripheral device, such as a network interface controller, shares and accesses the same set of address translation tables maintained by the host operating system, allowing direct access to the appropriate table using stored reference information to translate virtual memory addresses into physical addresses, thereby enabling efficient execution of work items without the need for dedicated memory translation tables within the I/O device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If I/O devices use dedicated memory translation tables, then address translation can be performed independently, but device complexity and memory overhead increase
Solution Approach 1:
The patent merges the address translation functionality of I/O devices with the host OS address translation tables. Instead of maintaining separate translation tables in the I/O device, the system combines these functions by allowing the I/O device to access and utilize the host OS's existing translation tables directly, thereby eliminating redundant structures while maintaining translation efficiency
Solution Approach 2:
The host OS address translation tables are designed to serve multiple purposes: they function as the primary address translation mechanism for the host system while simultaneously serving as the translation resource for I/O devices. This multi-functionality eliminates the need for dedicated I/O translation tables, reducing overall system complexity
2Measurement precision
If I/O devices coordinate with host operating system for address translation, then translation accuracy is maintained, but overhead and data transfer latency increase
Solution Approach 1:
The system performs preliminary actions by pre-establishing shared access to address translation tables between the I/O device and host OS. The I/O device is given direct access permissions to the translation tables before data transfer operations begin, eliminating the need for repeated coordination requests during actual data transfer and reducing latency
Solution Approach 2:
The patent introduces an intermediary mechanism where the I/O device can directly access the host OS address translation tables through a controlled interface. This intermediary arrangement allows the I/O device to obtain accurate translations without requiring constant high-level coordination with the host OS, reducing overhead while maintaining translation accuracy
3Speed
If I/O devices handle page faults independently, then processing speed improves, but reliability and consistency with host memory management decrease
Solution Approach 1:
The system implements feedback mechanisms where the I/O device monitors its own address translation operations and can detect when translation failures occur. When a page fault is detected, the I/O device automatically initiates the appropriate memory management actions and receives feedback from the host OS to confirm successful resolution, ensuring consistency while maintaining fast processing
Solution Approach 2:
The I/O device is empowered to handle its own page fault situations by directly accessing the address translation tables and implementing its own translation logic. This self-service capability allows the I/O device to process page faults at device speed while maintaining consistency with host memory management through shared access to the same translation tables and coordination protocols
Data Source
AI summary
A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.