Peripheral Device Chip Serial Interface Clock Source Stabilization
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Solution Overview
Problem
Existing methods for data transmission between a master controller and peripheral devices face inefficiencies when switching between normal and power-saving modes, leading to potential data loss due to clock source stabilization issues during mode transitions.
Innovation Solution
A serial interface transmitting method that includes a clock source selector, controller, and register selector within a peripheral device chip, which receives saving power signals to determine operational modes and manage data transmission between normal and power-saving modes, ensuring stable data transfer without loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the master controller sends a waking signal to restart the operational clock source of the peripheral device that is in the saving power mode, then the peripheral device can return to normal mode for utilization, but data transmission loss may occur because the clock source needs a period for stabilization before oscillations have stabilized
Solution Approach 1:
The patent applies preliminary action by having the master controller wait for a predetermined period after sending the waking signal before initiating data transmission. This waiting period allows the clock source to stabilize its oscillations in advance, ensuring that data transmission occurs only when the peripheral device is ready, thus preventing data loss while maintaining ease of operation
Solution Approach 2:
The patent implements beforehand cushioning by introducing a time buffer (waiting period) between the waking signal and data transmission. This buffer acts as a protective measure that accommodates the clock source stabilization requirement, cushioning against potential data transmission errors that would occur if communication started too early
2Use of energy by moving object
If the master controller turns off the operational clock source of the peripheral device to enter saving power mode, then power consumption is reduced, but the peripheral device cannot process or transmit data until awakened
Solution Approach 1:
The patent applies periodic action by implementing intermittent operation cycles where the peripheral device alternates between saving power mode (clock off) and normal mode (clock on). During idle periods, the device enters low-power state to conserve energy, and is periodically awakened for data transmission tasks, achieving a balance between power consumption and productivity through rhythmic operational patterns
Solution Approach 2:
The patent implements dynamics by making the clock source operational state adjustable and responsive to communication needs. The system dynamically transitions between clock-off (power-saving) and clock-on (operational) states based on whether data transmission is required, allowing the peripheral device to adapt its power consumption and productivity levels to match actual operational demands
3Speed
If data transmission is initiated before the clock source oscillations stabilize after waking from saving power mode, then communication responsiveness is improved, but data transmission loss occurs
Solution Approach 1:
The patent applies preliminary action by requiring the master controller to wait for clock source stabilization before initiating data transmission. This preliminary waiting period ensures the peripheral device's clock is ready to process data accurately, preventing information loss while maintaining efficient communication by not delaying transmission longer than necessary
Data Source
AI summary
The present invention discloses a serial interface transmitting method utilized in a serial interface for connecting between a master controller and a peripheral device. The serial interface transmitting method comprises receiving a saving power signal from the master controller, a peripheral clock source and a serial interface clock source for generating a clock source selection result, switching an operational mode of the peripheral device according to the clock source selection result, and transmitting a datum to a peripheral-device register or a serial interface register according to the saving power signal and the operational mode.