Peripheral Circuit Layout for Compact 3D Memory Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and reduced sizes, which poses challenges in integrating semiconductor devices with fine widths and spacing distances.
Innovation Solution
The semiconductor device incorporates a first peripheral circuit region at the same level or layer as the memory cell region, featuring structures such as cell and peripheral channel structures, bitlines, and gate electrodes, with specific configurations to reduce the overall size and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuit regions are disposed at the same level as memory cell regions, then integration density is improved and device size is reduced, but manufacturing complexity increases due to finer pattern requirements
Solution Approach 1:
The patent implements three-dimensional stacked channel structures where memory cell channels are arranged vertically in multiple levels. This vertical stacking allows the peripheral circuit region to be disposed at the same level as memory cell regions while maintaining sufficient spacing and electrical isolation, thereby reducing overall device footprint without compromising manufacturability through advanced lithography
2Productivity
If finer patterns are implemented to increase integration density, then device functionality is improved, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent divides the semiconductor device into distinct first and second structures stacked vertically. The first structure contains peripheral circuit regions with channel structures, while the second structure contains memory cell regions with stacked channel structures. This segmentation allows each region to be optimized independently, achieving high integration density without requiring uniformly fine patterns across the entire device
Solution Approach 2:
The patent employs nested stacking where the second structure (memory cell region) is disposed over the first structure (peripheral circuit region) in the vertical direction. Multiple channel structures are stacked within each region, creating a nested three-dimensional architecture that increases integration density while using conventional lithography dimensions
Data Source
AI summary
A semiconductor device includes a memory cell region and a peripheral circuit region adjacent the memory cell region in a first horizontal direction. The memory cell region includes cell channel structures extending in the first horizontal direction and spaced apart from each other in a vertical direction; a cell bitline extending in the vertical direction; and cell gate electrodes overlapping the cell channel structures in the vertical direction and extending in a second horizontal direction. The peripheral circuit region includes a peripheral channel structure extending in the first horizontal direction; a peripheral bitline extending in the vertical direction; and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in the second horizontal direction. At least one of the cell channel structures is at a same level as the peripheral channel structure in the vertical direction.