Peripheral Circuits Using Recess Gate Transistors for Leakage Control
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Solution Overview
Problem
The challenge in 3D memory devices is to reduce the size of peripheral circuits without sacrificing performance, as the increasing number of page buffers dominates chip area and channel leakage degradation limits device area shrinkage.
Innovation Solution
Incorporating a mix of recess gate transistors and flat gate transistors in peripheral circuits, where recess gate transistors are used in page buffers to shrink device size while maintaining leakage performance, and flat gate transistors are used in other circuits to reduce fabrication complexity and variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device area is reduced to increase memory density, then memory capacity increases, but channel leakage degradation occurs
Solution Approach 1:
The patent applies different gate structures to different transistor types within the same peripheral circuit: recess gate transistors are used for first-type transistors (where leakage control is critical) while flat gate transistors are used for second-type transistors. This local differentiation allows optimized leakage control in critical paths without sacrificing overall device density.
Solution Approach 2:
The peripheral circuit is segmented into different transistor types based on functional requirements. First-type transistors handling critical leakage paths use recess gate structures, while other transistors use flat gate structures, allowing differentiated optimization across the circuit.
2Area of moving object
If recess gate transistors are used to reduce device size, then area efficiency improves, but fabrication complexity increases
Solution Approach 1:
Instead of applying recess gate structures to all transistors, the patent selectively applies them only to first-type transistors where area efficiency is most critical. This localized application reduces the overall fabrication complexity compared to universal recess gate implementation.
Solution Approach 2:
The transistor population is segmented into first-type and second-type based on functional importance. This segmentation allows the more complex recess gate fabrication to be applied only where necessary, while simpler flat gate fabrication is used elsewhere.
Data Source
AI summary
In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.