Peripheral Command Queue Interrupt Mechanism
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Solution Overview
Problem
In peripheral interface controllers with high data bandwidth, providing control inputs from an external processor is challenging due to interface saturation, leading to idle periods and inefficiencies, especially when prioritizing data transfers.
Innovation Solution
Implementing a dual-command queue system within the peripheral component, allowing for high-priority transfers to interrupt low-priority ones at designated points, enabling quicker processing of higher-priority commands without repeating previous operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same internal interface is used for both data transfers and control communications, then the interface structure is simplified, but control inputs are locked out during data transfers causing idle periods
Solution Approach 1:
The patent segments the command processing into two separate queues: a low priority command queue for normal data transfer commands and a high priority command queue for urgent control inputs. This segmentation allows the peripheral component to process control inputs from the high priority queue without being blocked by data transfers in the low priority queue, thereby resolving the contradiction between simplified interface structure and control input efficiency.
2Adaptability or versatility
If a processor is included in the peripheral interface controller to reduce contention, then control flexibility is improved, but cost, space, and power consumption increase
Solution Approach 1:
The patent introduces an intermediary mechanism - the dual-queue command processing system with interruptible low priority commands. Instead of using a full processor, the high priority queue acts as an intermediary that can preempt low priority commands when urgent control inputs are received. This provides control flexibility similar to a processor while avoiding the cost, space, and power consumption penalties of actual processor inclusion.
3Productivity
If data transfers are performed continuously without interruption, then interface utilization is maximized, but higher priority transfers cannot be performed promptly
Solution Approach 1:
The patent implements dynamic command processing where the processing priority is not fixed but can change based on incoming commands. The low priority commands in the low priority queue are marked as interruptible, allowing the system to dynamically switch to processing high priority commands from the high priority queue when needed. After handling the high priority command, the system returns to the low priority queue to resume processing, thus maintaining high interface utilization while enabling prompt handling of higher priority transfers.
Data Source
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AI summary
In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.