Peripheral Completion Report Coalescing for Bus Transaction Reduction

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Solution Overview

Problem

High-performance computing systems face bottlenecks due to the large number of bus transactions required for transmitting completion reports from peripheral devices to host memory, leading to bandwidth consumption and performance issues.

Innovation Solution

Implementing a computer peripheral device with processing circuitry that reduces the size of completion reports by eliminating repetitive information and coalescing multiple reports into a single transaction, using timers to manage latency and throughput, and employing cyclic buffers with validity indicators to distinguish between iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If completion reports are transmitted individually from peripheral device to host memory, then data integrity is maintained, but the number of bus transactions increases leading to bandwidth consumption and performance degradation

Engineering Contradiction:
Improvesystem performanceVSAvoidnumber of bus transactions
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent combines multiple completion reports into a single aggregated completion report that can be transmitted in one bus transaction. The peripheral device accumulates multiple completion reports and merges them into one consolidated report containing information from multiple individual reports, thereby reducing the number of bus transactions while maintaining data integrity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary accumulation and aggregation of completion reports in the peripheral device before transmission to host memory. By preparing and combining multiple reports in advance, the system reduces the frequency of bus transactions and improves overall transmission efficiency.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If completion reports are reduced in size by omitting repetitive fields, then bandwidth is conserved, but the complexity of identifying identical fields across multiple reports increases

Engineering Contradiction:
Improvebandwidth consumptionVSAvoidcomplexity of identifying identical fields
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts and identifies identical fields from multiple completion reports that can be omitted in reduced reports. By taking out the common repetitive information and separating it from unique data, the system reduces the size of transmitted reports while managing complexity through systematic field identification and comparison.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If multiple completion reports are coalesced into a single transaction, then the number of bus transactions is reduced, but latency may increase due to accumulation time

Engineering Contradiction:
Improvebus transaction efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic control of report accumulation with configurable thresholds and timing mechanisms. The system can adjust the accumulation behavior based on system conditions, balancing between reducing transaction frequency and maintaining acceptable latency by allowing flexible control over when coalescing occurs.

Inventive Principle:
Principle #15Dynamics

4Quantity of substance

If completion reports are accumulated in a cyclic buffer, then memory usage is optimized, but data from previous iterations may be retained causing confusion without proper marking

Engineering Contradiction:
Improvememory usageVSAvoiddata integrity across iterations
Core Design Contradiction:
Quantity of substanceVSLoss of information

Solution Approach 1:

The patent uses validity indicators as markers to distinguish between data from different iterations in the cyclic buffer. These indicators act like color codes that allow the system to identify and process only valid, current iteration data while ignoring stale data from previous iterations, thereby maintaining data integrity without requiring additional memory.

Inventive Principle:
Principle #32Color changes

Data Source

PatentUS10642775B1Size reduction of completion notifications
Publication Date: 2020.05.05 MELLANOX TECHNOLOGIES LTD(IL)
  • US10642775B1 patent drawing
  • US10642775B1 patent drawing
  • US10642775B1 patent drawing

AI summary

A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.