Peripheral Conductive Pillars for Semiconductor Vertical Interconnects
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Solution Overview
Problem
The existing methods for forming vertical electrical interconnections in semiconductor packages, such as through-silicon vias (TSVs), are time-consuming, costly, and prone to defects due to void formation, which hinders the production efficiency and reliability of semiconductor devices.
Innovation Solution
The method involves forming conductive pillars in recessed regions around semiconductor die, which allows for vertical electrical interconnects without the need for conductive vias, using a process that includes creating a recessed region, depositing a conductive layer, and forming insulating layers to expose the conductive pillars for interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but production time increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from forming vias through the entire silicon thickness (3D through-hole approach) to forming conductive pillars only in the peripheral recessed regions (2D surface approach). This dimensional change eliminates the need for deep via drilling and filling, significantly reducing production time while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent segments the interconnection structure by forming conductive pillars only in the peripheral recessed regions rather than forming through-silicon vias across the entire device area. This segmentation allows selective formation of interconnects where needed, reducing overall process time and complexity.
2Reliability
If through-silicon vias (TSVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from forming vias through the entire silicon thickness (3D through-hole approach) to forming conductive pillars only in the peripheral recessed regions (2D surface approach). This dimensional change eliminates the need for deep via drilling and filling, significantly reducing production time while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent uses a sacrificial mandrel structure that is temporarily formed, filled with conductive material, and then removed. This disposable mandrel approach simplifies the overall manufacturing process by eliminating complex via formation steps, reducing equipment requirements, and lowering manufacturing costs while achieving the same electrical interconnection function.
3Reliability
If through-silicon vias (TSVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but device complexity increases
Solution Approach 1:
The patent transitions from forming vias through the entire silicon thickness (3D through-hole approach) to forming conductive pillars only in the peripheral recessed regions (2D surface approach). This dimensional change eliminates the need for deep via drilling and filling, significantly reducing production time while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent extracts the problematic via-filling process entirely by replacing it with peripheral conductive pillar formation. By removing the deep via drilling and conformal plating steps, the source of void formation is eliminated, ensuring reliable electrical connectivity without the defect-prone via filling process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances production efficiency, reduces manufacturing costs, and improves the reliability of semiconductor devices by providing effective vertical electrical interconnects while eliminating the need for costly and time-consuming via filling processes.
Implementation Method 1
forming a conductive layer over the semiconductor wafer and into the recessed region
Implementation Method 2
forming a conductive layer over the semiconductor wafer and into the recessed region
Data Source
AI summary
A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.