Peripheral Controller Multiplexer Asynchronous FIFO
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Solution Overview
Problem
Existing peripheral controllers for half-duplex communication struggle with asynchronous system and peripheral clocks, requiring separate FIFOs for transmission and reception, which increases gate count and complexity.
Innovation Solution
A peripheral controller with a multiplexer circuit and FIFO that uses electronically controllable switches to selectively route system and peripheral signals based on a single selection signal, allowing a single asynchronous FIFO to handle both transmission and reception, reducing gate count and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate FIFOs are used for transmission and reception in half-duplex communication, then communication reliability is improved, but device complexity and gate count increase
Solution Approach 1:
The patent merges the transmission and reception FIFOs into a single shared FIFO structure. The multiplexer circuit selectively connects the FIFO to either the system bus or peripheral bus based on operation mode, allowing one FIFO to serve dual purposes for both transmission and reception operations, thereby reducing gate count while maintaining communication reliability
Solution Approach 2:
The single FIFO is designed with multi-functionality to handle both transmission and reception operations. By using the multiplexer circuit to switch between different bus connections, the same FIFO structure performs different functions (transmission or reception) depending on the selected mode, eliminating the need for separate dedicated FIFOs for each function
2Quantity of substance
If separate FIFOs are used for transmission and reception, then data buffering capability is improved, but the number of components increases
Solution Approach 1:
The patent combines two separate FIFO buffering functions into a single shared FIFO structure. The multiplexer circuit enables this single FIFO to be connected to either the system bus or peripheral bus, allowing it to buffer data for both transmission and reception operations, thus maintaining adequate buffering capability while reducing the total number of components
3Device complexity
If a single FIFO is shared for transmission and reception, then device complexity is reduced, but signal routing complexity increases
Solution Approach 1:
The multiplexer circuit serves as an intermediary component that simplifies the signal routing control. Instead of requiring complex control logic to manage multiple separate FIFOs, the multiplexer provides a straightforward switching mechanism that selects between system bus and peripheral bus connections to the single shared FIFO, making the control simpler and more manageable
Data Source
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AI summary
A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.