Peripheral Device Data Processing Chain for Deterministic Execution
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Solution Overview
Problem
Computer-based data acquisition systems face performance issues due to operating system overhead, non-real-time execution, and insufficient processing power, limiting their ability to handle demanding applications deterministically and efficiently.
Innovation Solution
A system and method for transferring data directly between peripheral devices within a computer system, allowing for processing without routing through the host processor or memory, utilizing a system interconnect to enable flexible and customizable data processing between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is processed through the host processor in a computer-based DAQ system, then the processing can be performed with general-purpose computing resources, but the system suffers from operating system overhead and non-deterministic execution that limits real-time performance
Solution Approach 1:
The patent segments the processing architecture by introducing dedicated co-processor devices that handle specific processing tasks independently from the host processor. This segmentation allows critical real-time processing to occur on specialized hardware while the host processor handles higher-level tasks, thereby achieving deterministic execution for time-sensitive operations while maintaining overall system versatility.
Solution Approach 2:
The patent introduces co-processor devices as intermediary components between the data acquisition hardware and the host processor. These co-processors act as mediators that perform processing operations locally, reducing the burden on the host processor and ensuring deterministic execution for critical operations while maintaining flexibility through programmable processing capabilities.
2Productivity
If more processing power is added to handle demanding applications, then the system can process more data, but the operating system overhead and resource management issues prevent scalable performance improvement
Solution Approach 1:
The patent divides the processing workload across multiple independent co-processor devices rather than relying on a single host processor. Each co-processor can be optimized for specific processing tasks, allowing the system to scale processing capacity by adding specialized hardware components without increasing the complexity of the overall system architecture or operating system management.
Solution Approach 2:
The patent uses multiple co-processor devices that can be replicated and distributed throughout the system. Each co-processor implements the same or similar processing capabilities, allowing the system to scale processing power through replication of proven processing units rather than developing increasingly complex single-processor architectures.
3Reliability
If dedicated co-processors are used to offload processing tasks, then deterministic real-time processing is achieved, but the fixed connections between co-processor and I/O channels limit system flexibility
Solution Approach 1:
The patent implements dynamic reconfigurability in the co-processor architecture, allowing the connections and processing assignments between co-processors and I/O channels to be changed during operation. This dynamic capability enables the system to maintain deterministic execution by keeping critical processing paths fixed while allowing flexibility to reassign tasks and resources as application requirements change.
Solution Approach 2:
The patent designs co-processor devices with universal interfaces and processing capabilities that can handle multiple types of data and processing tasks. This multi-functionality allows a single co-processor architecture to serve various I/O channels and application requirements, providing both the deterministic execution of dedicated hardware and the flexibility of reconfigurable processing assignments.
Data Source
AI summary
Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.