Direct Peripheral Data Transfer Switch Architecture
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Solution Overview
Problem
Current computer systems face performance limitations in high-performance computing (HPC) environments due to the inefficiencies in data transfer between peripheral devices and central memory, leading to increased latency and memory usage, particularly in systems requiring high reliability and redundancy.
Innovation Solution
A computer system architecture that enables direct data transfers between multiple peripheral devices using DMA type controllers, with a switch facilitating command distribution and data transfer between components, allowing for optimized data processing and memory access without relying on central memory intermediation, and incorporating validation mechanisms for secure access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data transfers go through central memory, then system compatibility is maintained, but latency increases and memory usage increases
Solution Approach 1:
The patent introduces a switch as an intermediary component that enables direct data transfers between peripheral devices without routing through central memory. The switch manages the data transfer commands and coordinates between initiating and target peripheral devices, resolving the contradiction by providing a new intermediary path that maintains system compatibility while eliminating the latency penalty of central memory intermediation.
Solution Approach 2:
The patent segments the data transfer path by separating the function of data transfer initiation (performed by DMA controllers of peripheral devices) from the traditional central memory routing. This segmentation allows direct peer-to-peer communication between peripheral devices, reducing latency while preserving system compatibility through the coordinated action of multiple independent components.
2Reliability
If data transfers go through central memory, then system compatibility is maintained, but central memory usage increases
Solution Approach 1:
The switch acts as a mediator that enables peripheral devices to communicate directly, eliminating the need to route all data transfers through central memory. This reduces central memory usage while maintaining system compatibility through the switch's coordination of data transfer commands between peripheral devices.
Solution Approach 2:
The patent extracts the data transfer function from central memory by enabling peripheral devices to perform transfers directly between themselves. This extraction reduces the burden on central memory while preserving system compatibility through the coordinated action of peripheral DMA controllers and the switch.
3Ease of operation
If traditional DMA controllers are used, then peripheral device access is enabled, but system performance is limited
Solution Approach 1:
The patent merges the capabilities of multiple peripheral devices into a unified direct transfer system. By combining the DMA controllers of initiating and target peripheral devices with the switch coordination, the system achieves enhanced performance while maintaining ease of operation through automated command distribution and data transfer.
Solution Approach 2:
The initiating peripheral device prepares data transfer commands in advance and sends them through the switch to target devices before actual data transfer occurs. This preliminary action enables optimized data processing and memory access patterns, improving system performance while maintaining ease of operation through automated command distribution.
4Loss of time
If direct data transfers between peripheral devices are enabled, then latency decreases and memory usage decreases, but system complexity increases
Solution Approach 1:
The switch serves as a mediator that manages the complexity of direct data transfers between peripheral devices. By centralizing the coordination function in the switch, the system reduces latency and memory usage while containing the complexity increase within a dedicated component rather than distributing it across all devices.
Solution Approach 2:
The initiating peripheral device automatically generates and sends data transfer commands through the switch without requiring continuous processor intervention. This self-service capability reduces latency and memory usage while managing system complexity through automated command distribution and target device acknowledgment protocols.
Data Source
AI summary
The invention relates in particular to a computer system including peripheral devices (600) and at least one switch (605) connected to each device. A first device includes a means for initiating a control of direct access to memory areas, each one of which is associated with a separate element of the system. The switch includes a means for transmitting at least a portion of the control to each element. At least one element comprises a second device including a means for receiving at least one control of direct access to a memory area of said second device, said control being received from said first device via said switch, and a means for transmitting said received control to a component of said second device. Said system allows said first device to perform a direct data transfer to or from a memory of said first peripheral device from or to each element.