Peripheral ESD Protection Circuit Layout for Semiconductor Power Devices
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Solution Overview
Problem
Conventional semiconductor power device layouts with ESD protection circuits on the gate pad limit scalability, flexibility, and ESD ratings, particularly for smaller die sizes, leading to inadequate protection against electrostatic discharges and increased production costs.
Innovation Solution
The ESD protection circuits are reconfigured to be formed as dopant stripes on the peripheral regions of the semiconductor power device, allowing for adjustable widths, multiple stages, and integration with gate resistors, enabling improved ESD ratings and reduced gate leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are placed on the gate pad, then ESD protection is provided, but the ESD width is limited by the gate pad size which limits the ESD rating
Solution Approach 1:
The ESD protection circuit is extracted from the gate pad area and relocated to the peripheral region of the semiconductor device. This separation allows the gate pad to maintain its original function for gate connection while the ESD circuit operates independently in the peripheral region, enabling wider ESD protection structures without compromising gate pad functionality.
Solution Approach 2:
The ESD protection circuit is extended into the peripheral region along the perimeter of the device, utilizing the lateral dimension around the active area. This dimensional expansion allows the ESD circuit to achieve greater effective width and higher ESD ratings without increasing the active device area or compromising gate pad size.
2Area of stationary object
If the gate pad size is kept small for wire bonding, then active area is maximized, but ESD protection rating is limited
Solution Approach 1:
The ESD protection function is extracted from the gate pad structure and implemented as a separate circuit in the peripheral region. This allows the gate pad to remain small for wire bonding while the ESD circuit achieves adequate protection rating through extended peripheral layout with multiple Zener diode pairs.
Solution Approach 2:
The ESD protection capability is enhanced by utilizing the peripheral dimension around the active area rather than expanding the gate pad area. The ESD circuit extends along the perimeter, converting lateral peripheral space into effective ESD protection width without encroaching on the active device area.
3Reliability
If ESD circuit width is increased for higher ESD rating, then ESD protection improves, but die size must increase which increases production cost
Solution Approach 1:
The ESD circuit utilizes the peripheral region around the active device area, extending along the perimeter rather than expanding the central active area. This peripheral布局 allows the ESD circuit to achieve greater effective width and higher ratings while maintaining a compact die size, as the peripheral space does not increase the overall device footprint significantly.
Solution Approach 2:
The ESD protection circuit is segmented into multiple stages with multiple Zener diode pairs distributed along the peripheral region. This segmentation allows the ESD protection function to be achieved through distributed protection elements rather than a single large-width structure, enabling high ESD ratings within limited die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ESD protection flexibility and scalability, achieving lower leakage currents and better protection performance, particularly for smaller die sizes, while maintaining a better performance-to-cost ratio.
Implementation Method 1
a first number of pairs of doped polysilicon regions of opposite conductivity types extending between the gate metal and the source metal to form a first number of Zener diodes
Data Source
AI summary
A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.