Peripheral Gate Dielectric Layout for Flash Memory Leakage Control
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Solution Overview
Problem
In semiconductor structures, particularly in the peripheral region of flash memory substrates, the uneven thickness of the gate dielectric layer leads to leakage current issues due to the oxide layer being removed before forming the gate dielectric, resulting in a thinner edge thickness.
Innovation Solution
A semiconductor structure is designed with a substrate having a peripheral region defined by isolation structures, where an oxide layer is formed around the gate dielectric layer, ensuring a uniform thickness and preventing leakage current, and conductive spacers are added to the memory structure to enhance gate coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the oxide layer is removed before forming the gate dielectric layer in the peripheral region, then the gate dielectric layer can be formed in the opening defined by the isolation structure, but the gate dielectric layer thickness becomes uneven at the edge of the active area
Solution Approach 1:
The oxide layer is retained and not removed before forming the gate dielectric layer. This preliminary decision to keep the oxide layer in place serves as an underlying layer that ensures uniform thickness of the gate dielectric layer when subsequently formed, eliminating the thickness variation that would occur at the edges of the active area.
Solution Approach 2:
The oxide layer acts as an intermediary layer between the substrate and the gate dielectric layer. By keeping this intermediate layer, the patent ensures that the gate dielectric layer maintains uniform thickness across the entire active area, including the edges, thereby resolving the thickness uniformity issue.
2Productivity
If the gate dielectric layer thickness is thinner at the edge of the active area, then the device can be manufactured with the oxide layer removed, but leakage current occurs during device operation
Solution Approach 1:
The oxide layer is preserved as a preliminary measure to prevent leakage current. By not removing the oxide layer before gate dielectric layer formation, the patent ensures that the gate dielectric layer achieves sufficient and uniform thickness at the edges of the active area, thereby preventing leakage current during device operation.
Solution Approach 2:
The oxide layer serves as a cushioning layer that prevents leakage current before it can occur. By maintaining this layer underneath the gate dielectric layer, the patent provides a protective buffer that ensures reliable electrical isolation, preventing leakage current issues during device operation.
Data Source
AI summary
Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.