Peripheral Initialization Register for Soft Reset of IP Modules
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Solution Overview
Problem
Current system-on-chip (SoC) designs face challenges in implementing a run-time soft-reset mechanism for independent peripheral interface modules, particularly in shared and distributed DMA systems, where ongoing transactions may stall due to non-responsive modules, leading to system hangs and potential stale transactions during reset.
Innovation Solution
A system-on-chip integrated circuit with a peripheral initialization register and a false acknowledge circuit, where each module has a bit for normal or reset mode, and a direct memory access unit prioritizes and manages data transactions, preventing writes to change module states during uncompleted transactions and generating acknowledge signals to prevent system hangs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a soft-reset mechanism is implemented for IP modules, then selective reset of individual modules is achieved, but system hangs may occur due to non-acknowledgement by resetting modules
Solution Approach 1:
The patent introduces a false acknowledge circuit as an intermediary component that generates acknowledge signals on behalf of IP modules during reset operations. This mediator prevents system hangs by ensuring that resetting modules do not block the DMA system, while still allowing selective reset of individual IP modules without affecting system-wide operation.
2Reliability
If IP modules are reset during ongoing transactions, then module errors are cleared, but stale transactions may be encountered by modules after reset
Solution Approach 1:
The patent implements a mechanism where the DMA system checks transaction completion status before allowing IP modules to exit reset mode. This preliminary action ensures that all ongoing transactions are properly completed or aborted before the module resumes normal operation, preventing stale transactions from being encountered after reset.
3Reliability
If entire system reset is performed for IP module errors, then error recovery is achieved, but system productivity is reduced due to complete shutdown
Solution Approach 1:
The patent implements segmentation by allowing independent reset of individual IP modules rather than requiring a complete system reset. The DMA system can selectively reset specific peripheral modules while maintaining operation of other modules, thus recovering from errors locally without shutting down the entire system and preserving overall productivity.
Data Source
AI summary
A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.