Peripheral Interconnects with Dummy Vias for Alignment
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Solution Overview
Problem
The scaling of memory devices is constrained by design rules that limit feature sizes and interconnects, necessitating the development of methods to further scale interconnects while minimizing masks and reducing resistance, while maintaining compatibility between peripheral and core areas.
Innovation Solution
The integration of a substrate with a peripheral area and core area, featuring a first and second inter-level dielectric layer, peripheral contacts, vias, and dummy vias, which are fabricated using a method that includes depositing and etching layers to form enlarged contacts and vias with improved alignment tolerances and manufacturability, allowing for concurrent fabrication with core area structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If interconnects are scaled down to achieve smaller minimum feature sizes, then device density and storage capacity increase, but manufacturing precision and alignment tolerances deteriorate
Solution Approach 1:
The patent introduces dummy vias in advance during the fabrication process to improve via alignment. These dummy vias are formed concurrently with actual vias through the same etching process, providing reference structures that enhance alignment precision without requiring additional masking steps. This preliminary action addresses the alignment tolerance issue before it becomes a critical manufacturing challenge.
Solution Approach 2:
The dummy vias act as intermediary reference structures between the lithography pattern and the final via formation. By providing these intermediate reference points, the patent enables better alignment control during the via etching process, effectively mediating the alignment tolerance problem that arises from scaling down interconnect dimensions.
2Ease of manufacture
If the number of masks is reduced to simplify fabrication, then manufacturing complexity decreases, but manufacturing precision may deteriorate
Solution Approach 1:
The patent merges the formation of dummy vias and actual vias into a single etching step that is performed concurrently. Both types of vias are created through the same process sequence using the same mask, eliminating the need for separate masking steps. This merging approach maintains manufacturing simplicity while ensuring precise alignment through the reference function of dummy vias.
Solution Approach 2:
The dummy vias serve multiple functions: they act as alignment reference structures, maintain process compatibility with actual vias, and are formed using the same fabrication steps. This multi-functionality allows the patent to reduce mask count while preserving manufacturing precision, as the dummy vias fulfill both reference and structural roles within the unified fabrication process.
3Quantity of substance
If via spacing is reduced to increase via density, then interconnect density increases, but manufacturing precision deteriorates
Solution Approach 1:
The dummy vias are formed in advance alongside actual vias through concurrent etching processes. These pre-formed dummy structures provide spatial reference points that enable better control over via spacing, allowing higher via density to be achieved while maintaining manufacturing precision through the reference framework established by the dummy vias.
Data Source
AI summary
An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.