Peripheral Interconnection Structure for 3D Memory Integration
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Solution Overview
Problem
The challenge in semiconductor devices, particularly in NAND flash memories, is to increase the degree of integration while reducing the area of interconnection structures for three-dimensionally arranged memory cells, which existing technologies have not effectively addressed.
Innovation Solution
A semiconductor device with a peripheral interconnection structure comprising an upper and lower interconnection structure, where the upper interconnection has a greater thickness than the lower interconnection, and the upper barrier layer does not cover the side surfaces of the upper interconnection, while the lower barrier layer covers the side surfaces of the lower interconnection, allowing for improved electrical characteristics and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interconnection structure area is reduced to increase integration, then the degree of integration is improved, but the electrical characteristics and structural stability deteriorate
Solution Approach 1:
The patent transitions from planar interconnection structures to three-dimensional vertically stacked interconnection structures. Multiple interconnection layers are stacked in the vertical direction, allowing increased integration capacity without expanding the horizontal area, while maintaining electrical performance through optimized vertical pathways and barrier layer configurations.
Solution Approach 2:
The patent applies different barrier layer configurations to different interconnection structures based on their specific requirements. The upper interconnection structure has a barrier layer only at the bottom surface, while the lower interconnection structure has barrier layers covering both bottom and side surfaces. This localized differentiation optimizes electrical characteristics for each structure's specific function and position.
2Productivity
If the interconnection structure area is reduced to increase integration, then the degree of integration is improved, but the warpage increases
Solution Approach 1:
The patent uses the lower interconnection structure with comprehensive barrier layer coverage (bottom and side surfaces) to counterbalance the warpage induced by the upper interconnection structure. The barrier layers in the lower structure provide structural support and stress distribution that compensates for the area reduction and maintains overall structural stability against warpage.
Solution Approach 2:
The patent intentionally creates asymmetric barrier layer configurations between upper and lower interconnection structures. The lower structure has more extensive barrier layer coverage than the upper structure, creating an asymmetric design that specifically addresses the warpage issue while maintaining integration benefits.
3Reliability
If the upper interconnection thickness is increased to improve electrical characteristics, then the electrical conductivity is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection system into distinct upper and lower structures with different thickness specifications. The upper interconnection has greater thickness for optimal electrical performance, while the lower interconnection has standard thickness. This segmentation allows each structure to be optimized independently without increasing overall manufacturing complexity, as the different thicknesses are established through separate formation processes.
Data Source
AI summary
A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.