Peripheral Interface Circuit with Data Buffer for Non-Continuous Address Access
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Solution Overview
Problem
Existing peripheral interface circuits face reduced data access speed when data addresses are not continuous, and they struggle to recognize new peripheral memories, leading to inefficiencies in accessing and identifying connected memory devices.
Innovation Solution
A peripheral interface circuit with an interface sequencer, input/output controller, register unit, and data buffer that checks for target data in the buffer before accessing the peripheral memory, allowing for faster data access and flexible identification of connected memory types by maintaining a copy of peripheral memory data and using valid bits and tags for address management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a FIFO buffer is used to store pre-fetched data for faster access, then data access speed is improved for continuous addresses, but data access speed is reduced when addresses are not continuous due to premature data removal from the buffer
Solution Approach 1:
The patent creates a copy of peripheral memory data in a buffer memory, allowing the system to serve data from the fast buffer when available while maintaining the ability to access the original peripheral memory. This copying mechanism enables the system to achieve fast access speeds without being constrained by the sequential access limitations of FIFO buffers when dealing with non-continuous addresses.
2Reliability
If the peripheral interface circuit performs identification of connected peripheral memory, then compatibility with existing memory is ensured, but the circuit cannot recognize new peripheral memory after it is implemented
Solution Approach 1:
The patent implements a dynamic identification mechanism where the peripheral interface circuit can adapt to both existing and new peripheral memory types. The circuit uses a state machine that can be programmed to recognize different memory types through configuration registers, allowing it to dynamically adjust its behavior based on the connected memory device rather than being fixed to a single identification protocol.
3Speed
If a data buffer is added to store copies of peripheral memory data, then data access speed is enhanced, but device complexity increases
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the peripheral memory and the bus master. This intermediary serves multiple functions: it stores copies of peripheral memory data for fast access, manages data validation through valid bits, and coordinates access through a state machine. By centralizing these functions in a dedicated intermediary component, the patent avoids scattering complexity across multiple separate modules while achieving enhanced data access speed.
Data Source
AI summary
A peripheral interface circuit and a peripheral memory system are provided. The peripheral interface circuit includes an interface sequencer, an input/output controller, a register unit and a data buffer. The interface sequencer receives requests from the input/output controller and accesses the peripheral memory in response to the requests. The data buffer is randomly accessed by address. If target data of the data access request exists in the data buffer, the input/output controller returns data from the data buffer in response to the request; if target data of the data access request does not exist in the data buffer, the input/output controller sends an interface request to the interface sequencer to access the peripheral memory and keeps a copy of at least the target data in the data buffer.