Peripheral Interface Circuit for Serial Memory Round Trip Delay
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Solution Overview
Problem
Next-generation microcontrollers with stacked serial memory experience slow Input/Output (I/O) pads due to high round trip delay, affecting data sampling efficiency.
Innovation Solution
A peripheral interface circuit with a finite state machine introduces a delay state before the read data state to absorb round trip delay, using a clock module to synchronize the pad return clock and sampling logic to sample and hold data from the data bus, and a sampling queue to resynchronize write and read pointers, ensuring accurate data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If stacked serial memory is embedded in microcontrollers to reduce silicon size, then device integration and compactness are improved, but round trip delay increases causing slow I/O pads
Solution Approach 1:
The finite state machine introduces a delay state before the read data state to pre-absorb the round trip delay. This preliminary action ensures that when data is returned from the stacked serial memory, the I/O pad is already ready to sample it correctly, eliminating the timing issue caused by the physical distance in stacked memory architecture.
2Measurement precision
If delay state is introduced to absorb round trip delay, then data sampling accuracy is improved, but operation cycles increase
Solution Approach 1:
The delay state is implemented as a periodic control mechanism within the finite state machine, where the pad return clock is delayed by a fixed number of cycles corresponding to the round trip delay. This periodic delay is applied consistently to each read operation, ensuring accurate sampling without requiring variable or excessive delay cycles.
3Measurement precision
If pad return clock is delayed to synchronize with memory read operation, then data sampling timing is improved, but clock synchronization complexity increases
Solution Approach 1:
The clock module is integrated with the finite state machine to combine the delay control functionality. Instead of separate delay circuits and clock management units, the pad return clock delay is controlled directly by the finite state machine's delay state, merging the timing control and clock synchronization into a single unified control structure.
Data Source
AI summary
A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.