Peripheral Logic Circuits Under DRAM Arrays
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Solution Overview
Problem
Contemporary DRAM memory devices have not achieved significant reduction in overall die size due to the lack of proportional reduction in peripheral circuitry, despite shrinking wordline and digit line pitches, leading to inefficient use of memory cell space.
Innovation Solution
Implementing peripheral circuit logic under the DRAM memory array, utilizing architectural designs such as Traditional, Quilt, and Quilt II, which involve placing support circuitry like sense amplifiers and sub-word line drivers under the memory array, and using tungsten interconnects to reduce metal line sizes and increase circuitry density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuitry size is reduced proportionally with memory cell pitch, then overall die size reduction is achieved, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The patent moves peripheral circuitry from the planar dimension (side-by-side with memory array) to the vertical dimension (underneath the memory array), utilizing the third dimension to reduce overall die footprint while maintaining manufacturing processability through established fabrication techniques
Solution Approach 2:
The patent nests peripheral circuitry within the footprint of the memory array by placing it underneath, allowing the peripheral circuits to occupy space that would otherwise be wasted, thereby reducing the overall die size without increasing manufacturing complexity
2Ease of manufacture
If peripheral circuits are placed outside the memory array, then manufacturing is simpler, but die size reduction is limited
Solution Approach 1:
The patent transitions from horizontal placement (peripheral circuits outside the array) to vertical placement (peripheral circuits underneath the array), utilizing the vertical dimension to achieve die size reduction while maintaining manufacturing simplicity through standard fabrication processes
3Quantity of substance
If tungsten interconnects are used to reduce metal line sizes, then circuitry density increases, but manufacturing cost increases
Solution Approach 1:
The patent changes the material parameter from traditional copper or aluminum interconnects to tungsten, enabling smaller line sizes and higher circuitry density while managing cost through selective application in critical areas where size reduction is most beneficial
Data Source
AI summary
Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.