Peripheral Memory Contacts With Oval Layout to Prevent Shorts
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Solution Overview
Problem
The increasing height of semiconductor devices results in deeper openings for contacts, leading to larger cross-sections and a higher risk of short circuits during etching, which is undesirable for reducing chip size and maintaining high data reliability and low power consumption.
Innovation Solution
The semiconductor device employs conductive contact portions with oval-shaped cross-sections, where the long diameter aligns with the direction of the interconnects, and the short diameter is less than the sum of the interconnect width and interval, preventing short circuits by ensuring adequate spacing between adjacent interconnects, and using multiple etching steps to form these contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the height of semiconductor devices is increased, then the device capacity and integration are improved, but the openings for contacts become deeper resulting in larger cross-sections and higher risk of short circuits
Solution Approach 1:
The contact opening cross-section is designed with asymmetric dimensions: the first dimension (width) is controlled to be smaller than the second dimension (length). This asymmetric shape allows the contact to fit through deeper openings while maintaining adequate spacing between adjacent contacts, thus preventing short circuits despite increased device height and capacity.
2Area of stationary object
If the distance between signal lines is reduced, then chip size is reduced, but the risk of short circuits increases
Solution Approach 1:
The asymmetric contact opening shape (narrower in the first dimension, longer in the second dimension) enables closer spacing between adjacent signal lines while maintaining reliable electrical isolation. This allows chip size to be reduced without proportionally increasing short circuit risk.
Solution Approach 2:
The contact opening has different dimensional characteristics in different directions: a smaller width in the first dimension for reduced spacing, and a larger length in the second dimension for adequate etching margin. This local differentiation of geometric properties optimizes both chip size and reliability.
3Length of stationary object
If deeper etching is performed to form contacts, then contacts can be formed in taller devices, but the openings result in larger cross-sections
Solution Approach 1:
The etching process creates asymmetric opening cross-sections where the width (first dimension) is intentionally made smaller than the length (second dimension). This asymmetric geometry allows deeper etching to be performed without the cross-sectional area increasing proportionally, as the narrower width compensates for the increased depth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short circuits between adjacent interconnects, allowing for the formation of contacts with smaller cross-sections, thereby reducing the risk of short circuits and enabling the creation of smaller, more reliable semiconductor devices with improved power efficiency.
Implementation Method 1
To form contacts, opening are created by etching layers above the substrate
Data Source
AI summary
Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming first interconnects; forming first dielectric layers above the first interconnects in a peripheral region; removing portions of the first dielectric layers to form first openings through the first dielectric layers in the peripheral region to expose the first interconnects at bottoms of the first openings; depositing first conductive material in the peripheral region to form first contact portions in the first openings; forming second dielectric layers on the first dielectric layers and the first contact portions in the peripheral region; removing second portions of the second dielectric layers to form second openings through the second dielectric layers to expose the first contact portions at bottoms of the second openings; depositing second conductive material to form a plurality of second contact portions in the corresponding first openings; and forming second interconnects on the second contact portions.