Peripheral Memory Controller Direct Data Transfer

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Solution Overview

Problem

Modern computer systems face performance limitations in data transfer between peripheral devices, particularly in high-performance computing environments, where DMA type controllers are used but can lead to memory access bottlenecks and inefficiencies.

Innovation Solution

A controller and method for direct memory access between peripheral devices, enabling direct data transfer between memories of multiple peripheral devices via a communication bus, with features for command initiation, validation, and protection, allowing authorized access and reducing central memory usage and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If DMA type controllers are used for data transfer between peripheral devices and central memory, then data transfer capability is improved, but memory access bottlenecks and system performance limitations occur

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidmemory access latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a communication bus as an intermediary between peripheral devices, enabling direct data transfer without routing through central memory. The bus acts as a mediator that allows DMA controllers of different peripheral devices to communicate and transfer data directly, eliminating the bottleneck of central memory access while maintaining DMA-based transfer capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the data transfer path by creating a dedicated communication channel (bus) separate from the central memory access path. This segmentation allows data to flow directly between peripheral devices through the bus, bypassing the central memory bottleneck while preserving the DMA transfer mechanism for cases where central memory access is still needed.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If central memory is used for all data transfers, then data transfer between peripheral devices is possible, but central memory requirements increase and processor efficiency decreases

Engineering Contradiction:

Improvedata transfer flexibilityVSAvoidcentral memory requirements

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The communication bus serves as an intermediary that enables direct peripheral-to-peripheral data transfer, reducing the need for central memory as an intermediate storage location. This maintains transfer flexibility while decreasing central memory requirements by eliminating unnecessary data routing through central memory.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the data transfer function from the central memory system by introducing a dedicated communication bus between peripheral devices. This extraction allows data to be transferred directly between peripherals without occupying central memory resources, thereby reducing central memory requirements while preserving transfer capability.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If direct access commands are allowed between peripheral devices, then data transfer efficiency is improved, but memory protection and security control become more difficult

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidmemory protection

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through the communication bus that enable validation and control of direct access commands between peripheral devices. The bus system provides feedback signals that allow the system to monitor and control data transfers, ensuring that memory protection requirements are met while maintaining efficient direct access capability.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The communication bus serves multiple functions: it enables direct data transfer between peripherals, provides validation control for access commands, and maintains protection mechanisms. This multi-functionality allows the system to achieve both high transfer efficiency and reliable memory protection through a single integrated solution.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8990451B2Controller for direct access to a memory for the direct transfer of data between memories of several peripheral devices, method and computer program enabling the implementation of such a controller

Publication Date: 2015.03.24 LE COMMISSARIAT À LÉNERGIE ATOMIQUE & AUX ÉNERGIES ALTERNATIVES

AI summary

The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means (425) for initiating at least one command for direct access to a region of a memory external to said first peripheral and means (400) for receiving at least one command for direct access to a region of a memory of said first peripheral, said command being received from said at least one second peripheral, and means (415) for transmitting said at least one received direct access command to a component of said first peripheral. The controller thus allows a controller of direct access to a memory of said at least one second peripheral to carry out a direct transfer of at least one data item to or from a memory of said first peripheral from or to said second peripheral.