Peripheral Memory Safety for Multi-Core Platforms
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Solution Overview
Problem
Existing memory safety mechanisms for languages like C and C++ are inefficient due to the overhead of handling fat pointers, which triple the size of pointers and require significant CPU modifications, making them prohibitive for use in multi-core platforms.
Innovation Solution
A memory safety peripheral using low-fat pointers that verifies pointer consistency without CPU modifications, allowing for efficient memory access and protection against buffer overflows and ROP attacks, utilizing a compiler to translate code and send pointer data to the peripheral for checking, and encoding meta data within pointers to enable flexible and scalable memory safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fat pointers are used to ensure memory safety, then memory safety is improved, but pointer size and handling overhead increase significantly
Solution Approach 1:
The pointer validation function is segmented from the CPU core and placed in a separate peripheral device. This allows the CPU to continue executing instructions without waiting for validation, while the peripheral independently checks pointer bounds in parallel, thus maintaining memory safety without blocking execution flow.
Solution Approach 2:
A dedicated memory safety peripheral acts as an intermediary between the CPU and memory system. This peripheral receives pointer information from the CPU, performs validation checks against stored bounds, and returns validation results, thereby offloading the complex validation logic from the CPU and reducing handling overhead.
2Reliability
If CPU modifications are made to implement memory safety checks, then memory safety verification is improved, but compatibility with existing CPU architectures and ease of deployment deteriorate
Solution Approach 1:
The memory safety functionality is segmented into a separate peripheral device rather than being integrated into the CPU core. This modular approach allows the peripheral to implement memory safety checks independently, maintaining full compatibility with existing CPU architectures while adding safety capabilities.
Solution Approach 2:
The memory safety peripheral serves as an intermediary layer between the CPU and memory system, providing safety verification without requiring modifications to the CPU itself. The peripheral intercepts memory access requests, validates pointers against stored bounds, and allows or blocks access accordingly, thus preserving CPU architecture compatibility.
3Reliability
If comprehensive pointer validation is performed, then memory safety is improved, but execution speed and productivity deteriorate due to validation overhead
Solution Approach 1:
Pointer bounds information is pre-calculated and stored in the memory safety peripheral before execution. During runtime, the peripheral simply compares current pointers against these pre-stored bounds rather than performing complex validation calculations, thus maintaining thorough validation while minimizing execution overhead.
Solution Approach 2:
The memory safety peripheral acts as an intermediary that performs validation in parallel with CPU execution. By handling validation independently and concurrently, the peripheral does not block the CPU execution flow, thereby maintaining both comprehensive validation and high execution speed.
Data Source
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AI summary
A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds.