Peripheral Module Register Access for Efficient Data Transfers
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Solution Overview
Problem
The inefficiency in data transfers between higher-bit-width processor cores and lower-bit-width data registers in peripheral modules due to the need for multiple access instructions, which consumes processor cycles and complicates backward compatibility.
Innovation Solution
Implementing additional x-bit programming model locations within the peripheral module that are mapped to existing y-bit programming model resources, allowing for more efficient data transfers by executing fewer instructions and reducing processor cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple access instructions are used to transfer data between higher-bit-width processor cores and lower-bit-width data registers, then data transfer can be performed, but processor cycles are consumed and transfer efficiency deteriorates
Solution Approach 1:
The peripheral module's data register address space is segmented into multiple regions, each mapped to different bit-width access interfaces. This allows the processor to select an appropriate access width matching its native bus width, eliminating the need for multiple sequential access instructions and reducing processor cycle consumption.
2Productivity
If additional x-bit programming model locations are mapped to existing y-bit programming model resources, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The peripheral module is designed with multi-functional address mapping capability, where a single data register can be accessed through multiple address locations with different bit-width interpretations. This universal access mechanism enables both 8-bit and 32-bit processors to efficiently access the same hardware resource without requiring separate physical registers, balancing improved productivity with controlled complexity.
Data Source
AI summary
An embodiment of an electronic system includes a processing element, a bus controller, and a peripheral module. The processing element executes machine readable code for performing a data transfer of an x-bit wide data value between the processing element and the peripheral module. Performing the data transfer includes providing a processing element-provided address corresponding to a y-bit wide data register of the peripheral module, where y is less than x. The bus controller receives the processing element-provided address, and in response, performs a series of multiple data transfers with the peripheral module. This includes providing a first peripheral address for a first data transfer of the series, and providing at least one different peripheral address for at least one other data transfer of the series. The peripheral module maps the first peripheral address and the at least one different peripheral address to the y-bit wide data register.