Peripheral Package-on-Package Interconnect Etching
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing smaller, higher-density semiconductor devices with improved electrical interconnection and packaging, which are essential for smaller footprints and increased performance.
Innovation Solution
A method involving a temporary carrier with conductive interconnects formed around a semiconductor die, encapsulated with a mold compound, and subsequent etching and grinding processes to expose ends of the interconnects, allowing for build-up interconnect structures and enabling package-on-package stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor packaging processes are used, then manufacturing simplicity is maintained, but device density and electrical interconnection performance deteriorate
Solution Approach 1:
The packaging process is segmented into distinct stages: forming conductive interconnects in peripheral areas, mounting semiconductor dies, encapsulating with mold compound, and selective etching to expose interconnect ends. This segmentation allows complex high-density interconnections to be achieved through manageable, sequential steps rather than attempting to create all interconnections simultaneously.
Solution Approach 2:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical stacking by forming conductive interconnects that extend vertically through the mold compound. This enables package-on-package stacking where multiple semiconductor packages are vertically interconnected, dramatically increasing device density without proportionally increasing footprint area.
2Area of moving object
If smaller semiconductor devices are produced, then footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Conductive interconnects are formed in the peripheral areas of the semiconductor wafer before the dies are mounted and encapsulated. This preliminary formation of interconnect structures allows precise positioning and formation of conductive paths while the wafer is still in a manageable state, before subsequent processing steps that would make further interconnect formation more difficult.
Solution Approach 2:
The mold compound serves as an intermediary medium that encapsulates both the semiconductor dies and the conductive interconnects. This intermediary material provides structural support, electrical insulation, and a controlled environment for forming precise interconnections, while the selective etching of the mold compound later exposes the interconnect ends for bonding to subsequent packages.
3Adaptability or versatility
If vertically oriented electrical interconnects are formed, then package-on-package stacking is enabled, but manufacturing process complexity increases
Solution Approach 1:
The conductive interconnects formed in the peripheral areas serve multiple functions: they provide electrical connection between stacked packages, act as structural support elements within the mold compound, and define the bonding interfaces for subsequent packages. This multi-functionality reduces the need for separate specialized structures for each function.
Solution Approach 2:
The selective etching process automatically exposes the ends of conductive interconnects that are positioned at the top surface of the mold compound after encapsulation. This self-service mechanism ensures that interconnect ends are precisely exposed where needed for bonding to subsequent packages without requiring additional complex positioning or alignment steps.
4Reliability
If peripheral areas are used for conductive interconnects, then electrical interconnection is improved, but usable die area is reduced
Solution Approach 1:
The wafer perimeter area is segmented and dedicated exclusively to forming conductive interconnect structures, while the central area is dedicated to mounting semiconductor dies. This spatial segmentation allows the peripheral region to be fully utilized for creating reliable vertical interconnections without encroaching on the active die area, as the interconnects are formed in the empty peripheral space before die mounting.
Data Source
AI summary
A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive interconnects over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted at the semiconductor die mounting site. The conductive interconnects and semiconductor die can be encapsulated with mold compound. First ends of the conductive interconnects can be exposed. The temporary carrier can be removed to expose second ends of the conductive interconnects opposite the first ends of the conductive interconnects. The conductive interconnects can be etched to recess the second ends of the conductive interconnects with respect to the mold compound. The conductive interconnects can comprise a first portion, a second portion, and an etch stop layer disposed between the first portion and the second portion.