Peripheral Package-on-Package Device with Backside RDL
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing smaller semiconductor devices with higher density and efficiency, particularly in achieving smaller footprint and reducing warpage during processing, while maintaining effective electrical interconnection and packaging.
Innovation Solution
A method involving a temporary carrier with a semiconductor die mounting site, forming an insulating layer and conductive pads, and a backside redistribution layer (RDL) to facilitate vertical electrical interconnects, followed by encapsulation with a mold compound and subsequent grinding to expose conductive pads, allowing for a build-up interconnect structure and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional semiconductor packaging processes are used, then manufacturing simplicity is maintained, but device footprint cannot be reduced and warpage occurs during processing
Solution Approach 1:
The patent applies preliminary action by forming the backside redistribution layer (RDL) and conductive interconnects on the temporary carrier before mounting the semiconductor die. This advance preparation of interconnection structures enables subsequent packaging steps to be simplified while achieving reduced footprint through the fully molded configuration.
Solution Approach 2:
The patent transitions from conventional planar packaging to a three-dimensional fully molded structure where the mold compound encapsulates the entire assembly including vertical conductive interconnects extending through the package height, enabling PoP stacking and reduced footprint by utilizing the vertical dimension for electrical connections.
2Stability of the object's composition
If conventional packaging processes are used, then process simplicity is maintained, but warpage occurs during processing
Solution Approach 1:
The patent employs composite materials by combining the semiconductor die, temporary carrier, mold compound, and conductive interconnects into a fully encapsulated assembly. The mold compound acts as a stress-distributing matrix that reduces warpage by providing uniform mechanical support throughout the package structure during and after processing.
3Productivity
If smaller semiconductor devices are produced, then power consumption decreases and performance increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses the temporary carrier as an intermediary substrate that provides a stable platform for forming precise conductive interconnects and mounting the semiconductor die. The carrier enables accurate positioning and alignment of interconnection structures before final encapsulation, achieving high manufacturing precision for small devices while maintaining efficient production through wafer-level processing.
Data Source
AI summary
A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.