Peripheral Power Domains With Event-Driven Wake-Up Logic
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Solution Overview
Problem
Existing peripheral interconnects in integrated-circuit devices result in significant power wastage due to inefficient communication between peripherals and the processor, leading to suboptimal power management.
Innovation Solution
Implementing a peripheral interconnect system with wake-up logic that enables event signaling between peripherals in different power domains, allowing peripherals to be powered down while still receiving event signals, and using distributed programmable peripheral interfaces (DPPI) to facilitate direct communication among peripherals, reducing the need for processor involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If peripherals are powered down to save power, then power consumption is reduced, but the ability to receive event signals is lost
Solution Approach 1:
The system divides the peripheral interconnect functionality into two distinct pathways: a low-power mode where only essential wake-up logic remains active, and a full-power mode for normal operation. This segmentation allows the peripheral to be powered down while maintaining minimal circuitry capable of receiving and routing event signals, thus resolving the contradiction between power savings and signal reception capability
Solution Approach 2:
A wake-up logic intermediary is introduced between the peripheral interconnect and the powered-down peripheral. This intermediary component remains active in low-power mode, monitoring event signals and conditionally waking up the peripheral when relevant events occur. The wake-up logic acts as a mediator that preserves the peripheral's ability to respond to events without requiring the entire peripheral to remain powered on continuously
2Reliability
If the processor remains awake to handle peripheral communication, then communication reliability is maintained, but power consumption increases
Solution Approach 1:
The peripheral interconnect system is designed to be self-service capable by implementing automatic event routing and peripheral wake-up management without requiring processor intervention. The wake-up logic autonomously monitors event channels, determines which peripherals need to be activated, and manages the power state transitions, thereby maintaining communication reliability while allowing the processor to enter sleep mode and reduce power consumption
Solution Approach 2:
The wake-up logic serves as an intermediary layer between the peripheral interconnect and the processor, handling communication coordination and peripheral activation tasks. This intermediary absorbs the communication management burden, enabling the processor to remain in low-power states while still maintaining reliable peripheral communication through the wake-up logic's coordinated control
3Productivity
If a peripheral interconnect is implemented to enable direct peripheral communication, then communication efficiency is improved, but power wastage occurs due to continuous operation
Solution Approach 1:
The peripheral interconnect system implements dynamic power management by allowing peripherals to transition between active and sleep states based on communication needs. The wake-up logic dynamically activates peripherals only when event signals indicate necessary communication, and deactivates them during idle periods. This dynamic state management maintains high communication efficiency when needed while minimizing power consumption during idle times
Solution Approach 2:
Instead of continuous operation, the system employs periodic activation of peripherals based on event-driven triggers. The wake-up logic monitors event channels periodically and activates peripherals only when relevant events occur, rather than maintaining continuous operation. This periodic action pattern preserves communication efficiency by ensuring peripherals are active when needed while significantly reducing power wastage during idle intervals
Data Source
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AI summary
An integrated-circuit device(100)comprises first and second peripherals(122, 124, 26, 128), connected to a processor (102) via a bus system(110), a peripheral interconnect(160)that is separate from the bus system, wake up logic(150), a configuration memory and a power controller(106). In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response, The first peripheral(122, 124), second peripheral (126, 128) and the wake-up logic(150)are in a first(142), second (144) and third (148) power domain respectively. The power controller(106)provides power to the third power domain(148)whenever the first or second power domain is powered up. The wake-up logic(150)detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral. With Figure