Peripheral Power Control via Hardware Handshaking

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Solution Overview

Problem

Multiprocessing systems face challenges in maximizing the use of on-chip peripherals while minimizing power consumption, as existing technologies lack efficient methods for dynamic allocation and quick transition to low power modes with minimal software overhead.

Innovation Solution

A hardware-controlled handshaking mechanism using peripheral enable bits for each core and peripheral allows for dynamic allocation and efficient communication of low power requests and acknowledgments, enabling cores and their allocated peripherals to transition to low power modes with minimal software overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dynamic allocation of peripherals is implemented to maximize usage, then peripheral utilization is improved, but system complexity increases

Engineering Contradiction:
Improveperipheral utilizationVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements automatic peripheral allocation and power mode management through hardware logic that monitors processor activity and autonomously configures peripheral assignments. The peripheral control logic automatically detects when processors enter low-power modes and相应地 adjusts peripheral power states without requiring software intervention, allowing the system to serve itself in managing resource allocation and power consumption.

Inventive Principle:
Principle #25Self-service

2Use of energy by moving object

If processors enter low power modes frequently, then power consumption is reduced, but transition time and software overhead increase

Engineering Contradiction:
Improvepower consumptionVSAvoidtransition time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent replaces software-based power mode management with a hardware-controlled system. The peripheral control logic is implemented in hardware, allowing automatic detection of processor power state transitions and immediate corresponding adjustments to peripheral power modes. This hardware-based approach eliminates software overhead and reduces transition latency, enabling rapid switching between power states without the delays associated with software polling and configuration.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If hardware-controlled handshaking is implemented for power mode transitions, then transition speed is improved, but control complexity increases

Engineering Contradiction:
Improvetransition speedVSAvoidcontrol complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the peripheral control functionality with the existing power management infrastructure by integrating peripheral enable bits into the processor's power mode control registers. The handshaking protocol is combined with the existing interrupt and acknowledgment mechanisms already present in the multiprocessing system. This consolidation allows the hardware-controlled power mode transitions to leverage existing control pathways and signaling infrastructure, reducing the need for separate dedicated control circuits and minimizing overall system complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10120435B2Multiprocessing system with peripheral power consumption control
Publication Date: 2018.11.06 NXP USA INC
  • US10120435B2 patent drawing
  • US10120435B2 patent drawing
  • US10120435B2 patent drawing

AI summary

An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.