Peripheral Register Refresh Sequencing With DMA Status Control
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Solution Overview
Problem
In real-time applications, refreshing peripheral registers using a direct memory access (DMA) system introduces significant latency and increased power consumption due to interrupt execution by the central processing unit (CPU).
Innovation Solution
Implementing a control register and status register in peripherals to manage an access sequence for refreshing specific registers, where the control register selects which registers to update and the status register tracks the sequence's completion, allowing for efficient DMA sequencing with minimal CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parameters are updated frequently using software and CPU, then the peripheral registers are refreshed accurately, but power consumption increases
Solution Approach 1:
The patent extracts the parameter update task from the CPU by implementing a dedicated DMA controller that autonomously handles peripheral register refreshing. The DMA controller is configured with control data indicating which registers to update, allowing it to operate independently without continuous CPU intervention, thus reducing power consumption while maintaining update accuracy.
Solution Approach 2:
The DMA controller is designed to self-manage the peripheral register update process by autonomously accessing data registers, refreshing target registers, and updating status registers based on control data. This self-service capability eliminates the need for CPU involvement in each update cycle, significantly reducing power consumption while ensuring reliable parameter updates.
2Ease of operation
If parameters are updated using software and CPU, then the refresh process is flexible and controllable, but latency is significant due to interrupt execution
Solution Approach 1:
The patent extracts the time-consuming interrupt handling and parameter update tasks from the CPU by implementing a dedicated DMA controller. This separate controller handles peripheral register refreshing autonomously based on pre-configured control data, eliminating interrupt execution delays and reducing update latency while maintaining operational flexibility through programmable control.
Solution Approach 2:
The DMA controller is pre-configured with control data that specifies which peripheral registers need updating before the actual refresh operation begins. This preliminary configuration allows the controller to execute updates immediately without waiting for CPU interrupts or software commands, significantly reducing latency while preserving control flexibility through the pre-set parameters.
3Ease of operation
If CPU is continuously involved in parameter updates, then the refresh process can be precisely controlled, but system performance decreases
Solution Approach 1:
The patent extracts the parameter update functionality from the main CPU by implementing a dedicated DMA controller. This separate unit handles all peripheral register refreshing operations autonomously based on pre-configured control data, freeing the CPU to focus on high-level control tasks and improving overall system performance while maintaining precise update control through the DMA's programmable interface.
Solution Approach 2:
The DMA controller autonomously manages the entire parameter update process by self-configuring based on control data, self-executing the register refreshes, and self-updating status registers. This self-service operation eliminates the need for continuous CPU involvement, improving system performance while maintaining precise control over which registers are updated and when.
Data Source
AI summary
Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.