Peripheral Scan Dump via Memory-Mapped I/O for Remote Debugging
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Solution Overview
Problem
Debugging peripheral devices, especially in complex SoC systems, is challenging due to disruptive scan dump methods and the unavailability of JTAG connectors, which can lead to mission mode disruptions and soft locks, making it difficult to identify root causes of failures, especially during production phases.
Innovation Solution
Implementing a scan dump mechanism that captures logic states using memory-mapped input/output (MMIO) access, allowing for remote debugging over a network connection, thereby bypassing JTAG connectors and enabling continuous mission mode operation, even when the base CPU platform experiences failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional scan dump methods are used to capture logic states, then debugging information can be obtained, but mission mode functionality is disrupted
Solution Approach 1:
The patent segments the debugging functionality from the main mission mode operation by implementing a separate scan dump state machine that operates independently. The isolation wrapper divides the system into distinct components: the host interface for normal operation, the control interface for debugging, and the scan dump state machine for capturing logic states, allowing debugging without disrupting mission mode functionality.
Solution Approach 2:
The patent introduces an isolation wrapper as an intermediary component between the host interface and the scan dump state machine. This wrapper manages the interaction between debugging operations and mission mode functionality, ensuring that scan dump operations can capture logic states without causing disruptions to the primary system operation.
2Loss of information
If JTAG connectors are used for debugging, then logic states can be captured, but the system enters soft lock mode and local debugging is inhibited
Solution Approach 1:
The patent extracts the scan dump functionality from the traditional JTAG connector dependency by implementing a memory-mapped I/O based debugging interface. The host interface can initiate scan dump operations through memory-mapped I/O commands, eliminating the need for physical JTAG connector access and allowing debugging to continue even when the base CPU platform experiences failures that would normally cause soft lock mode.
3Measurement precision
If step-in debugging is performed, then individual instructions can be analyzed, but the process is time-consuming and impractical for complex SoC systems
Solution Approach 1:
The patent implements preliminary action by capturing a complete snapshot of all logic states in the SoC system before analysis begins. The scan dump state machine captures the state of all flip-flops and logic elements simultaneously, providing a comprehensive view of the system state that can then be analyzed without time-consuming step-by-step debugging, significantly reducing the time required to diagnose issues in complex SoC systems.
Data Source
AI summary
A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.