Peripheral Circuit TFT Geometry for Breakdown Voltage Stability
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Solution Overview
Problem
The breakdown voltage in oxide semiconductor TFTs used for peripheral circuits in liquid crystal display panels varies, leading to potential dielectric breakdown and current leakage, which is not a concern for pixel TFTs due to lower source-drain voltage.
Innovation Solution
An active matrix substrate design with TFTs in the peripheral circuit region having a specific geometry where the source and drain electrode regions overlap the gate electrode but not the oxide semiconductor layer, with the source and drain electrode lengths in the channel width direction being smaller than the oxide semiconductor layer, and the drain electrode entirely overlapping the gate electrode, while the source electrode only partially overlaps, to stabilize the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the gate electrode and drain electrode are arranged offset from each other to improve breakdown voltage, then the breakdown voltage increases, but the on-current decreases and the TFT area increases due to auxiliary gate electrode
Solution Approach 1:
The invention applies different overlap configurations to different regions: the source electrode region has partial overlap with the gate electrode while the drain electrode region has complete overlap. This local differentiation allows the drain side to achieve high breakdown voltage through complete overlap, while the source side maintains good on-current through partial overlap, resolving the contradiction between these two requirements.
2Reliability
If the oxide semiconductor layer length in channel width direction is made greater than source and drain electrode lengths to improve electrostatic protection, then breakdown voltage against static electricity increases, but the TFT area increases
Solution Approach 1:
The invention optimizes the parameters by setting the source and drain electrode lengths in the channel width direction to be equal to or slightly less than the oxide semiconductor layer length, rather than making the semiconductor layer significantly longer. This parameter optimization achieves adequate electrostatic protection while minimizing the TFT area, resolving the contradiction between reliability and area.
3Power
If higher source-drain voltage is applied to peripheral circuit TFTs to improve driving capability, then the driving capability increases, but dielectric breakdown occurs and current leakage increases
Solution Approach 1:
The invention applies complete overlap between drain electrode and gate electrode specifically at the drain side where high voltage stress occurs during peripheral circuit operation. This local quality enhancement at the critical drain region provides the necessary dielectric breakdown resistance to handle higher source-drain voltages while maintaining driving capability.
Data Source
AI summary
An active matrix substrate of an embodiment includes a plurality of TFTs provided in a peripheral circuit region. The plurality of TFTs includes a TFT (10A) in which, when viewed in a direction perpendicular to a substrate (11A), a length in the channel width direction of a source electrode region (15AR) and a length in the channel width direction of a drain electrode region (16AR), WAs and WAd, are each smaller than a length in the channel width direction of the oxide semiconductor layer (14A), WAos, the length in the channel width direction of the oxide semiconductor layer (14A), WAos, is smaller than a length in the channel width direction of a gate electrode (12A), WAg, and a region in which at least one of the source electrode region (15AR) and the drain electrode region (16AR) is in contact with the oxide semiconductor layer(14A) entirely overlaps the gate electrode (12A).