Same Size Die Stacked Package With Peripheral Through-Hole Vias

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Solution Overview

Problem

Current through-hole via (THV) technology in semiconductor devices limits the placement of additional circuitry within the device and reduces yields due to the need for wider saw streets when vias are located outside the semiconductor device.

Innovation Solution

The implementation of a THV stackable semiconductor device with integrated cavities and peripheral surface vias connected through metal traces, allowing for stacked semiconductor packages of the same size without the limitations of traditional THV technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a via is located within a semiconductor device, then the device can be stacked with other devices, but the placement of additional circuitry within the device is restricted

Engineering Contradiction:
Improveplacement flexibility of circuitryVSAvoiddevice functionality limitation
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent moves the via location from the traditional planar dimension (within the die active area) to the peripheral dimension (along the saw street guide at the edge of the die). This dimensional relocation allows the active die area to remain fully available for circuitry placement while still enabling via formation for stacking capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If a via is located outside the semiconductor device along the saw street guide, then additional circuitry can be placed within the device, but wider saw streets are required which reduces wafer yields

Engineering Contradiction:
Improvewafer yieldVSAvoidsaw street width
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by concentrating the via formation process specifically along the saw street guide region rather than requiring wide saw streets across the entire wafer. This localized approach allows standard-width saw streets to suffice, maintaining wafer yield while enabling peripheral via placement for enhanced circuitry flexibility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7750452B2Same size die stacked package having through-hole vias formed in organic material
Publication Date: 2010.07.06 JCET SEMICON (SHAOXING) CO LTD
  • US7750452B2 patent drawing
  • US7750452B2 patent drawing
  • US7750452B2 patent drawing

AI summary

A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.