Peripheral Transistor Level Configuration for Memory Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and large capacity while maintaining operational reliability, particularly in three-dimensional designs where space is limited and efficient transistor arrangement is crucial.
Innovation Solution
The semiconductor memory device incorporates a unique structure with a cell source structure, alternately stacked insulating and conductive patterns, and peripheral transistors arranged in a specific level configuration, allowing for a higher density of peripheral transistors within a limited space, enhancing operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If peripheral transistors are arranged at the same level as the cell source structure, then the number of peripheral transistors per unit area increases, but the manufacturing complexity increases due to multi-level doping requirements
Solution Approach 1:
The patent applies dimensionality change by arranging peripheral transistors at different vertical levels relative to the cell source structure. Specifically, some peripheral transistors are positioned at the same level as the cell source structure while others are positioned at a lower level, utilizing the vertical dimension to increase transistor density without requiring all transistors to be at the same plane. This multi-level arrangement allows more peripheral transistors to be integrated into the same planar footprint.
Solution Approach 2:
The patent segments the peripheral transistor arrangement into multiple groups positioned at different vertical levels. The first group of peripheral transistors is arranged at the same level as the cell source structure, while the second group is arranged at a lower level. This segmentation enables independent optimization of each group's positioning and reduces the complexity of simultaneous multi-level doping by allowing sequential or selective processing.
2Area of stationary object
If peripheral transistors are arranged at different levels, then space utilization improves, but the manufacturing precision requirements increase for aligning structures at different levels
Solution Approach 1:
The patent employs preliminary action by forming the lower-level peripheral transistors before forming the cell source structure and upper-level peripheral transistors. This sequential approach allows each level to be precisely formed and aligned independently, with subsequent levels built upon established reference structures. The preliminary formation of lower-level transistors creates a stable foundation that simplifies the alignment and positioning of upper-level structures.
Solution Approach 2:
The patent implements a nested structure where peripheral transistors at different levels are vertically aligned and nested relative to each other. The lower-level peripheral transistors are positioned beneath the cell source structure and upper-level peripheral transistors, creating a vertically nested arrangement. This nesting allows precise alignment to be achieved through vertical stacking rather than complex lateral positioning, reducing manufacturing precision requirements.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure.