Peripherally Placed TSVs for Crack Containment in Semiconductor Chips
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Solution Overview
Problem
Conventional semiconductor chips with through-silicon-vias (TSVs) face issues such as Joule heating, electromigration, and mechanical stresses during dicing and mounting, which can lead to crack propagation and damage to the delicate circuit structures, especially due to the lack of effective crack containment and thermal expansion mismatches.
Innovation Solution
The implementation of peripherally placed TSVs connected to die seals on both sides of the semiconductor chip, providing enhanced mechanical strength and acting as electrical pathways, while also serving as crack stops to prevent propagation and reinforce the chip against thermal and mechanical stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSVs are used with one-to-one arrangement to bump pads, then electrical routing between opposite surfaces is achieved, but the chip is subjected to Joule heating and electromigration issues
Solution Approach 1:
The patent divides the TSV arrangement into multiple groups where each TSV connects to multiple bump pads rather than a one-to-one arrangement. This segmentation distributes the electrical current and thermal load across multiple connection points, reducing Joule heating and electromigration effects on individual TSVs while maintaining reliable electrical routing.
2Productivity
If dicing operation is performed to cut individual dice from wafer, then individual semiconductor dice are obtained, but significant stresses and impact loads cause microscopic fractures particularly at die corners
Solution Approach 1:
The patent performs preliminary reinforcement by forming a die seal structure around the periphery of the semiconductor die before the dicing operation. This pre-formed seal provides mechanical support and stress distribution during cutting, preventing microscopic fractures at die corners while still allowing individual dice to be produced from the wafer.
3Reliability
If conventional crack stop structure is used that does not extend to die edges, then crack propagation is partially addressed, but cracks can achieve significant length before encountering the crack stop and become uncontrollable
Solution Approach 1:
The patent employs an asymmetric crack stop design where the die seal extends to and integrates with the die edges, creating an asymmetric structure that provides continuous crack containment from all directions. This asymmetric extension to the edges ensures cracks cannot achieve critical length without encountering the seal, improving reliability while managing complexity through integrated design.
4Adaptability or versatility
If stacked semiconductor chips are mounted to address functionality without increasing package area, then vertical stacking is achieved, but significant bending stresses occur due to thermal expansion mismatches
Solution Approach 1:
The patent modifies the thermal and mechanical parameters of the chip structure by forming a die seal that extends to the periphery and integrates with TSVs. This seal structure changes the overall thermal expansion characteristics and provides mechanical reinforcement that reduces bending stresses in stacked configurations, enabling higher functionality density without excessive stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances the mechanical strength and electrical functionality of semiconductor chips, reduces crack propagation, and improves thermal management by stiffening the chip and providing a robust framework against bending moments and thermal cycling, thereby protecting the internal circuit structures.
Implementation Method 1
Each through-silicon-via includes a first end connected to and in ohmic contact with the first die seal and a second end connected to and in ohmic contact with the second die seal
Implementation Method 2
The peripherally placed TSVs provide enhanced mechanical strength for the semiconductor chip and serve as crack stops to prevent propagation
Implementation Method 3
improves thermal management by stiffening the chip and providing a robust framework against bending moments and thermal cycling
Data Source
Figure 1~2
Figure 3~4
Figure 5~7
AI summary
A method of manufacturing includes connecting a first end (131) of a first through-silicon- via (100f) to a first die seal (125) proximate a first side of a first semiconductor chip (15). A second end (133) of the first thu-silicon-via is connected to a second die seal (115) proximate a second side of the first semiconductor chip opposite the first side.