Peripheral TSVs for PoP Stacked Die Electrical Connectivity
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Solution Overview
Problem
The semiconductor industry faces challenges in forming through-silicon vias (TSVs) for 3D ICs and stacked dies, particularly near device regions, which can lead to device degradation and significant area usage, necessitating alternative structures and methods for providing electrical connections and heat dissipation in package on package structures.
Innovation Solution
The formation of through sidewall vias (TsVs) by sawing through the substrate, which are separated from device regions and located at the edges of semiconductor dies, along with the use of redistribution structures and copper posts, enables efficient electrical connections between dies without degrading device performance and optimizes area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are formed near device regions for electrical connections in 3D ICs, then electrical connectivity between stacked dies is improved, but device degradation occurs and significant area is consumed
Solution Approach 1:
The patent extracts the via formation process from the device region and relocates it to the peripheral region. TsVs are formed exclusively in the peripheral region surrounding the device region, separating the via formation activity from the sensitive device area. This extraction eliminates the harmful effects of via formation on device performance while maintaining electrical connectivity function.
Solution Approach 2:
The patent transitions from a conventional vertical via structure to a sidewall via structure where vias are formed along the sidewalls of trenches in the peripheral region. This dimensional reconfiguration allows electrical connections to be established through the sidewalls rather than through the center of the device region, achieving connectivity without device degradation.
2Reliability
If through-silicon vias (TSVs) are formed for electrical connections in stacked dies, then electrical connectivity is achieved, but significant area is consumed
Solution Approach 1:
The patent segments the substrate into distinct device region and peripheral region, with vias confined to the peripheral region. This segmentation allows the device region to be optimized for active device area while the peripheral region handles the electrical interconnection function, thereby reducing overall area consumption compared to conventional TSV approaches that require larger device region area.
3Productivity
If conventional packaging technologies are used, then manufacturing processes are established, but integration density cannot be increased further
Solution Approach 1:
The patent implements package on package (PoP) architecture where a first packaged device is stacked vertically on top of a second packaged device, transitioning from planar to three-dimensional integration. This vertical stacking enables increased integration density without requiring further reduction in feature size or complexity in conventional planar manufacturing processes.
Data Source
AI summary
Various embodiments of mechanisms for forming a die package using through sidewall vias (TsVs), which are formed by sawing through substrate via (TSV) in half, at edges of dies described enable various semiconductor dies and passive components be electrically connected to achieve targeted electrical performance. Redistribution structures with redistribution layers (RDLs) are used along with the TsVs to enable the electrical connections. Since the TsVs are away from the device regions, the device regions do not suffer from the stress caused by the TSV formation. In addition, electrical connections between upper and lower dies by the TsVs increases the efficiency of the area utilization of the die package.