Peripheral Unit Direct Virtual Access Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data processing systems require additional software components like arbitrators to manage access to peripheral units, which can impact performance and security, and are vulnerable to failures or malicious actions from virtual units.

Innovation Solution

A peripheral unit is designed to be simultaneously accessible by multiple virtual processing units through a unique entry point, using register sets to allocate and manage access requests without the need for additional software components, allowing for efficient and secure service execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional software components like arbitrators are used to manage access to peripheral units, then access control and security are improved, but system performance deteriorates and device complexity increases

Engineering Contradiction:
Improveaccess control securityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the arbitrator software component from the system and replaces it with a hardware-based peripheral unit that directly manages access control. This removes the performance bottleneck caused by software-based arbitration while maintaining security through hardware-level authentication and authorization mechanisms.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the software-based mechanical arbitration process with a hardware-level solution. The peripheral unit uses hardware registers, state machines, and direct memory access capabilities to manage access control, eliminating the need for software arbitrators and improving system performance.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If additional software components like arbitrators are used to manage access to peripheral units, then access control and security are improved, but device complexity increases

Engineering Contradiction:
Improveaccess control securityVSAvoidsoftware component complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the complex software arbitrator component entirely and replaces it with a simplified hardware-based peripheral unit. This extraction of the arbitration function to hardware level reduces software complexity while maintaining access control capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The peripheral unit is designed to be self-managing, using its own hardware resources (registers, state machines, memory) to handle access control decisions. This self-service capability eliminates the need for external software arbitrators and reduces overall system complexity.

Inventive Principle:
Principle #25Self-service

3Device complexity

If a unique entry point is used for peripheral access, then device complexity is reduced, but concurrent access management becomes more difficult

Engineering Contradiction:
Improveaccess interface complexityVSAvoidconcurrent access efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the access management function by creating multiple independent access paths through the single entry point. Each virtual processing unit has its own access request queue and state machine, allowing concurrent access management despite the unique entry point.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic access management where the peripheral unit can dynamically switch between different virtual processing units based on real-time needs. The state machine dynamically transitions between different access states, enabling efficient concurrent access control.

Inventive Principle:
Principle #15Dynamics

4Productivity

If virtual processing units can directly access peripheral units, then system performance is improved, but security risks and reliability issues increase

Engineering Contradiction:
Improveaccess speedVSAvoidsystem security
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces the peripheral unit's hardware-based access control mechanism as an intermediary between virtual processing units and the actual peripheral resources. This intermediary layer provides authentication and authorization while allowing direct access when permitted, balancing performance and security.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements beforehand cushioning by requiring virtual processing units to pre-authenticate and obtain access rights before executing operations. The hardware state machine verifies permissions in advance, preventing unauthorized access and ensuring system security before performance-critical operations occur.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8782304B2Method for enabling several virtual processing units to directly and concurrently access a peripheral unit
Publication Date: 2014.07.15 MICROELECTRONIC INNOVATIONS LLC
  • US8782304B2 patent drawing
  • US8782304B2 patent drawing
  • US8782304B2 patent drawing

AI summary

The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.