Periphery Interconnect Package Layout for Low-Interference Chip Coupling
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Solution Overview
Problem
The existing packages with integrated devices and substrates face performance issues due to adverse electrical coupling between integrated devices, which affects the overall performance and efficiency of the package.
Innovation Solution
The package design incorporates a substrate with dielectric layers, interconnects, a solder resist layer, and periphery interconnects located over the solder resist layer, allowing for electrical coupling between integrated devices through these periphery interconnects, which are strategically placed along the boundary of the routing and keep-out regions to improve power distribution network performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated devices are electrically coupled through the substrate, then signal transmission is enabled, but electrical interference and performance degradation occur
Solution Approach 1:
The substrate is divided into a central region and a periphery region with distinct functions. The central region contains traditional interconnects for substrate-level connections, while the periphery region contains periphery interconnects specifically for device-to-device coupling. This segmentation separates different electrical paths and reduces interference between them.
Solution Approach 2:
Periphery interconnects act as intermediary elements located at the boundary between the central and periphery regions. These interconnects provide dedicated electrical paths for coupling integrated devices without requiring signals to traverse through the central substrate region, thereby reducing electrical interference and improving signal integrity.
2Reliability
If traditional interconnect routing is used, then electrical coupling is achieved, but the area and number of metal layers increase
Solution Approach 1:
The patent utilizes the periphery region of the substrate, which is typically underutilized space, to place additional interconnects. By routing signals along the periphery rather than through the central area, the design effectively uses the boundary dimension of the substrate to reduce the overall area required for interconnect routing.
Solution Approach 2:
Different regions of the substrate are assigned different functions: the central region handles substrate-level interconnections while the periphery region handles device-to-device couplings. This local differentiation allows optimized routing paths that reduce the total area and metal layer requirements compared to uniform interconnect distribution.
Data Source
AI summary
A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.