Periphery Transistor Staging for Nonvolatile Memory Cell Isolation
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Solution Overview
Problem
In nonvolatile memory arrays, neighboring memory cells experience unwanted stress conditions during operations like writing, erasing, or reading due to shared word lines and bit lines, leading to incorrect value changes, and existing solutions require sophisticated circuit designs to prevent this, which can fail due to high leakage currents and parasitic capacitance from driving transistors and testing devices.
Innovation Solution
The use of one or more stages of periphery transistors with optimized characteristics, such as reduced gate and junction capacitance, and leakage currents, is implemented to mitigate these issues by revising the mask layer to connect word lines with different types of periphery transistors, allowing for improved testing and manufacturing of memory arrays with enhanced transistor conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high gate-to-channel electric field is applied to erase selected memory cells, then erase operation is effective, but neighboring memory cells may be inadvertently erased due to electric field disturbance
Solution Approach 1:
Periphery transistors are introduced as intermediary components between the word line and neighboring memory cells. These transistors act as mediators that can selectively gate the electric field, allowing high field application to selected cells while blocking field propagation to neighboring cells through controlled transistor switching states.
Solution Approach 2:
The patent applies different electrical conditions to different spatial locations within the memory array. By controlling periphery transistors, the system creates localized high electric field regions at selected memory cells while maintaining low field conditions at neighboring cells, enabling spatially differentiated erase operations.
2Reliability
If periphery transistors with optimized characteristics are used, then disturbance to neighboring memory cells is reduced, but device complexity increases due to additional transistor stages
Solution Approach 1:
The patent employs dynamically controllable periphery transistors whose characteristics can be adjusted during operation. By dynamically switching transistor states and optimizing their electrical characteristics based on operational requirements, the system achieves reliable neighboring cell protection while managing complexity through adaptive control rather than static over-engineering.
Data Source
AI summary
Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).